Changes in RISCVAsmBackend.cpp

412c788a - [NFC][Alignment] Use Align in MCAlignFragment

Tue, 14 Jun 2022 11:31:58 +0000

[NFC][Alignment] Use Align in MCAlignFragment List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

d09d297c - [RISCV] Fix crash for section alignment with .option norvc

Thu, 07 Apr 2022 11:00:41 +0000

[RISCV] Fix crash for section alignment with .option norvcThe existing code wasn't getting the subtarget info from the fragment,so the current status of RVC would be ignored. This would cause a crashfor the new test case when the target then reported it couldn't writethe requested number of code alignment bytes.Differential Revision: https://reviews.llvm.org/D122236 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

f15014ff - Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"

Wed, 26 Jan 2022 15:55:53 +0000

Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"This reverts commit ef8206320769ad31422a803a0d6de6077fd231d2.- It conflicts with the existing llvm::size in STLExtras, which will now never be called.- Calling it without llvm:: breaks C++17 compat List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

ef820632 - Rename llvm::array_lengthof into llvm::size to match std::size from C++17

Wed, 26 Jan 2022 15:11:12 +0000

Rename llvm::array_lengthof into llvm::size to match std::size from C++17As a conquence move llvm::array_lengthof from STLExtras.h toSTLForwardCompat.h (which is included by STLExtras.h so no buildbreakage expected). List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

e63455d5 - [MC] Use local MCSubtargetInfo in writeNops

Mon, 09 Aug 2021 10:40:22 +0000

[MC] Use local MCSubtargetInfo in writeNopsOn some architectures such as Arm and X86 the encoding for a nop maychange depending on the subtarget in operation at the time ofencoding. This change replaces the per module MCSubtargetInfo retainedby the targets AsmBackend in favour of passing through the localMCSubtargetInfo in operation at the time.On Arm using the architectural NOP instruction can have a performancebenefit on some implementations.For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo tolimit the chances of this causing problems in the future. I've notdone this for other targets such as X86 as there is more frequent useof the MCSubtargetInfo and it looks to be for stable properties thatwe would not expect to vary per function.This change required threading STI through MCNopsFragment andMCBoundaryAlignFragment.I've attempted to take into account the in tree experimental backends.Differential Revision: https://reviews.llvm.org/D45962 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

53f5f141 - fix an -Wunused-variable warning in release built, NFC

Thu, 17 Jun 2021 16:48:12 +0000

fix an -Wunused-variable warning in release built, NFC List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

bbea6425 - RISCV: adjust handling of relocation emission for RISCV

Wed, 26 May 2021 15:41:11 +0000

RISCV: adjust handling of relocation emission for RISCVThis re-architects the RISCV relocation handling to bring theimplementation closer in line with the implementation in binutils. Wewould previously aggressively resolve the relocation. With thisrestructuring, we always will emit a paired relocation for any symbolicdifference of the type of S±T[±C] where S and T are labels and C is aconstant.GAS has a special target hook controlled by `RELOC_EXPANSION_POSSIBLE`which indicates that a fixup may be expanded into multiple relocations.This is used by the RISCV backend to always emit a paired relocation -either ADD[WIDTH] + SUB[WIDTH] for text relocations or SET[WIDTH] +SUB[WIDTH] for a debug info relocation. Irrespective of whether linkerrelaxation support is enabled, symbolic difference is always emitted asa paired relocation.This change also sinks the target specific behaviour down into thetarget specific area rather than exposing it to the shared relocationhandling. In the process, we also sink the "special" handling for debuginformation down into the RISCV target. Although this improves the pathfor the other targets, this is not necessarily entirely ideal either.The changes in the debug info emission could be done through anothertype of hook as this functionality would be required by any other targetwhich wishes to do linker relaxation. However, as there are no othertargets in LLVM which currently do this, this is a reasonable thing todo until such time as the code needs to be shared.Improve the handling of the relocation (and add a reduced test case fromthe Linux kernel) to ensure that we handle complex expressions forsymbolic difference. This ensures that we correct relocate symbols withthe adddends normalized and associated with the addition portion of thepaired relocation.This change also addresses some review comments from Alex Bradbury aboutthe relocations meant for use in the DWARF CFA being named incorrectly(using ADD6 instead of SET6) in the original change which introduced therelocation type.This resolves the issues with the symbolic difference emissionsufficiently to enable building the Linux kernel with clang+IAS+lld(without linker relaxation).Resolves PR50153, PR50156!Fixes: ClangBuiltLinux/linux#1023, ClangBuiltLinux/linux#1143Reviewed By: nickdesaulniers, maskrayDifferential Revision: https://reviews.llvm.org/D103539 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

2d922de3 - [MC][RISCV] Support .reloc , BFD_RELOC_{NONE,32,64},

Sat, 06 Mar 2021 05:45:11 +0000

[MC][RISCV] Support .reloc *, BFD_RELOC_{NONE,32,64}, *BFD_RELOC_NONE is useful for ld --gc-sections: it provides a generic way indicating a dependency between two sections. List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

8bb059ab - [MC][Bugfix] Remove redundant parameter for relaxInstruction

Fri, 17 Apr 2020 12:26:26 +0000

[MC][Bugfix] Remove redundant parameter for relaxInstructionSummary:Before this patch, `relaxInstruction` takes three arguments, the firstargument refers to the instruction before relaxation and the thirdargument is the output instruction after relaxation. There are two quitestrange things: 1) The first argument's type is `const MCInst &`, the third argument's type is `MCInst &`, but they may be aliased to the same variable 2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third argument is a fresh uninitialized `MCInst` even if `relaxInstruction` may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a loop.In this patch, we drop the thrid argument, and let `relaxInstruction`directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, andbreaks the assumption of ARM, AMDGPU, RISC-V, Hexagon.Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcainReviewed By: Razer6, MaskRay, bcainSubscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D78364 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

a7aaaf70 - [MC][RISCV] Make .reloc support arbitrary relocation types

Sun, 29 Mar 2020 17:01:01 +0000

[MC][RISCV] Make .reloc support arbitrary relocation typesSimilar to D76746 (ARM), D76754 (AArch64) and llvmorg-11-init-6967-g152d14da64c (x86)Differential Revision: https://reviews.llvm.org/D77018 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

3f5976c9 - [RISCV] Fix evaluating %pcrel_lo against global and weak symbols

Thu, 23 Jan 2020 02:05:46 +0000

[RISCV] Fix evaluating %pcrel_lo against global and weak symbolsSummary:Previously, we would erroneously turn %pcrel_lo(label), where label hasa %pcrel_hi against a weak symbol, into %pcrel_lo(label + offset), asevaluatePCRelLo would believe the target independent logic was going tofold it. Moreover, even if that were fixed, shouldForceRelocation lacksan MCAsmLayout and thus cannot evaluate the %pcrel_hi fixup to a valueand check the symbol, so we would then erroneously constant-fold the%pcrel_lo whilst leaving the %pcrel_hi intact. After D72197, this samesequence also occurs for symbols with global binding, which is triggeredin real-world code.Instead, as discussed in D71978, we introduce a new FKF_IsTarget flag toavoid these kinds of issues. All the resolution logic happens in oneplace, with no coordination required between RISCAsmBackend andRISCVMCExpr to ensure they implement the same logic twice. Although theimplementation of %pcrel_hi can be left as target independent, we makeit target dependent to ensure that they are handled identically to%pcrel_lo, otherwise we risk one of them being constant folded but theother being preserved. This also allows us to properly support fixuppairs where the instructions are in different fragments.Reviewers: asb, lenary, efriedmaReviewed By: efriedmaSubscribers: arichardson, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D73211 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

41449c58 - [RISCV] Fix evaluation of %pcrel_lo

Fri, 08 Nov 2019 08:26:30 +0000

[RISCV] Fix evaluation of %pcrel_loThe following testcase function: .Lpcrel_label1: auipc a0, %pcrel_hi(other_function) addi a1, a0, %pcrel_lo(.Lpcrel_label1) .p2align 2 # Causes a new fragment to be emitted .type other_function,@function other_function: retexposes an odd behaviour in which only the %pcrel_hi relocation isevaluated but not the %pcrel_lo. $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - : file format ELF64-riscv Disassembly of section .text: 0000000000000000 function: 0: 17 05 00 00 auipc a0, 0 4: 93 05 05 00 mv a1, a0 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 0000000000000008 other_function: 8: 67 80 00 00 retThe reason seems to be that in RISCVAsmBackend::shouldForceRelocation weonly consider the fragment but in RISCVMCExpr::evaluatePCRelLo weconsider the section. This usually works but there are cases where thesection may still be the same but the fragment may be another one. Inthat case we end forcing a %pcrel_lo relocation without any %pcrel_hi.This patch makes RISCVAsmBackend::shouldForceRelocation use the section,if any, to determine if the relocation must be forced or not.Differential Revision: https://reviews.llvm.org/D60657 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

90b6bb75 - [MC] Minor cleanup to MCFixup::Kind handling. NFC.

Fri, 23 Aug 2019 01:00:55 +0000

[MC] Minor cleanup to MCFixup::Kind handling. NFC.Prefer `MCFixupKind` where possible and add getTargetKind() toconvert to `unsigned` when needed rather than scattering castoperators around the place.Differential Revision: https://reviews.llvm.org/D59890llvm-svn: 369720 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

1c1f8f21 - [RISCV] Don't force absolute FK_Data_X fixups to relocs

Mon, 19 Aug 2019 13:23:02 +0000

[RISCV] Don't force absolute FK_Data_X fixups to relocsThe current behavior of shouldForceRelocation forces relocations for themajority of fixups when relaxation is enabled. This makes sense forfixups which incorporate symbols but is unnecessary for simple datafixups where the fixup target is already resolved to an absolute value.Differential Revision: https://reviews.llvm.org/D63404Patch by Edward Jones.llvm-svn: 369257 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

18ccfadd - [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

Fri, 19 Jul 2019 02:03:34 +0000

[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.It is necessary to generate fixups in .debug_frame or .eh_frame asrelaxation is enabled due to the address delta may be changed afterrelaxation.There is an opcode with 6-bits data in debug frame encoding. So, wealso need 6-bits fixup types.Differential Revision: https://reviews.llvm.org/D58335llvm-svn: 366524 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

657277e0 - Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."

Thu, 18 Jul 2019 15:06:50 +0000

Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e.llvm-svn: 366444 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

e43ce1a9 - [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

Thu, 18 Jul 2019 14:47:34 +0000

[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.It is necessary to generate fixups in .debug_frame or .eh_frame asrelaxation is enabled due to the address delta may be changed afterrelaxation.There is an opcode with 6-bits data in debug frame encoding. So, wealso need 6-bits fixup types.Differential Revision: https://reviews.llvm.org/D58335llvm-svn: 366442 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

bb479ca3 - [RISCV] Avoid overflow when determining number of nops for code align

Tue, 16 Jul 2019 04:40:25 +0000

[RISCV] Avoid overflow when determining number of nops for code alignRISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign() assumed that thealign specified would be greater than or equal to the minimum nop length, butthat is not always the case - for example if a user specifies ".align 0" inassembly.Differential Revision: https://reviews.llvm.org/D63274Patch by Edward Jones.llvm-svn: 366176 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

e9ad0cf6 - [RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()

Tue, 16 Jul 2019 04:37:19 +0000

[RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()The bool result of shouldInsertExtraNopBytesForCodeAlign() is not checked butthe returned nop count is unconditionally read even though it could beuninitialized.Differential Revision: https://reviews.llvm.org/D63285Patch by Edward Jones.llvm-svn: 366175 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

44cc4e93 - [RISCV] Simplify RISCVAsmBackend::writeNopData(). NFC

Sat, 15 Jun 2019 06:14:15 +0000

[RISCV] Simplify RISCVAsmBackend::writeNopData(). NFCllvm-svn: 363486 List of files: /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp