en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#cfcac264 [CSKY] Support bitcast operation from/to double to/from two GPRsIn soft ABI, floating num is passing in GPRs. So we need supportbitcovert from double to Hi and Lo GPRs and vice versa List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Thu, 07 Apr 2022 10:24:34 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#989f1c72 Cleanup codegen includesThis is a (fixed) recommit of https://reviews.llvm.org/D121169after: 1061034926before: 1063332844Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanupDifferential Revision: https://reviews.llvm.org/D121681 List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Tue, 15 Mar 2022 09:54:19 +0000 serge-sans-paille <sguelton@redhat.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#a190fcdf [CSKY] Add inline asm constraints and related codegen supportThere are kinds of inline asm constraints and corresponding register class or register as following. 'b': mGPRRegClass 'v': sGPRRegClass 'w': sFPR32RegClass or sFPR64RegClass 'c': C register 'z': R14 register 'h': HI register 'l': LO register 'y': HI or LO registerIt also adds codegen test for inline-asm including constraints, clobbers and abi names. List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Mon, 07 Feb 2022 09:26:13 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#8ddc8169 [CSKY] Lower leaf DAG node such as global symbol, frame address and jumptable, etc.Lower global symbols such as call/external symbol.Lower other leaf DAG node such as frame address/block address/jumptable/vastart.Normally some leaf symbols need reside in constant pool as ABI prefers, and are addressed bylrw or jsri instructions.Every symbol in constant pool is lowered with one entry in target constant pool. Theentry has different type corresponding to different leaf node such as blockaddress,jumptable, or global value. List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Thu, 06 Jan 2022 09:21:49 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#9566cf16 [CSKY] Add codegen of select/br/cmp instruction and some frame lowering infraAdd basic integer codegen of select/br/cmp instruction. It also includes frame lowering codesuch as prologue/epilogue. List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Thu, 30 Dec 2021 08:10:22 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#a556ec88 [CSKY] Complete codegen of basic arithmetic and load/store operationsComplete basic arithmetic operations such as add/sub/mul/div, and it also includes converionsand some specific operations such as bswap.Add load/store patterns to generate different addressing mode instructions.Also enable some infra such as copy physical register and eliminate frame index. List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Thu, 09 Dec 2021 03:35:34 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp#cf78715c [CSKY] First patch to construct codegen infra and generate first add instructionOoops. It constructs codegen infra and provide only basic code to generate first add instruction successfully.Differential Revision: https://reviews.llvm.org/D112206 List of files: /llvm-project-15.0.7/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp Mon, 01 Nov 2021 02:06:56 +0000 Zi Xuan Wu <zixuan.wu@linux.alibaba.com>