en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#e0d585d7 AMDGPU: Defer creation of WWM VGPR spill slotsThere's no reason to create these immediately. They can be created inthe prolog/epilog code like CSR spills. There's probably a cleaner wayto do this by utilizing the CSR spill code.This makes the frame index used transient state forPrologEpilogInserter, and thus makes serialization easier. Really thisdoesn't need to be saved here but there isn't really a better placefor it. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Sat, 16 Apr 2022 13:27:49 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#4271ae22 AMDGPU: Remove some unreachable code in WWM passDefs must be registers and there's no point to code afterllvm_unreachable. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Sat, 16 Apr 2022 13:29:54 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#989f1c72 Cleanup codegen includesThis is a (fixed) recommit of https://reviews.llvm.org/D121169after: 1061034926before: 1063332844Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanupDifferential Revision: https://reviews.llvm.org/D121681 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Tue, 15 Mar 2022 09:54:19 +0000 serge-sans-paille <sguelton@redhat.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#a278250b Revert "Cleanup codegen includes"This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,and many LLVM tests, see comments on https://reviews.llvm.org/D121169 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Thu, 10 Mar 2022 12:54:41 +0000 Nico Weber <thakis@chromium.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#7f230fee Cleanup codegen includesafter: 1061034926before: 1063332844Differential Revision: https://reviews.llvm.org/D121169 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Mon, 07 Mar 2022 23:25:52 +0000 serge-sans-paille <sguelton@redhat.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#3366d811 [AMDGPU] Save WWM registers in functionsThe values of registers in inactive lanes needs to be saved duringfunction calls.Save all registers used for whole wave mode, similar to how it is donefor VGPRs that are used for SGPR spilling.Differential Revision: https://reviews.llvm.org/D99429Reapply with fixed tests on window. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Fri, 23 Apr 2021 14:09:31 +0000 Sebastian Neubauer <sebastian.neubauer@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#22d99cb6 Revert "[AMDGPU] Save WWM registers in functions"This reverts commit 91464c30bfcf731ccb7f9d6ef6d26e8c1657a6e6.Seems to break tests on windows. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Fri, 23 Apr 2021 14:38:23 +0000 Sebastian Neubauer <sebastian.neubauer@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#91464c30 [AMDGPU] Save WWM registers in functionsThe values of registers in inactive lanes needs to be saved duringfunction calls.Save all registers used for whole wave mode, similar to how it is donefor VGPRs that are used for SGPR spilling.Differential Revision: https://reviews.llvm.org/D99429 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Fri, 23 Apr 2021 14:09:31 +0000 Sebastian Neubauer <sebastian.neubauer@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#4672bac1 [AMDGPU] Introduce Strict WQM mode* Add amdgcn_strict_wqm intrinsic.* Add a corresponding STRICT_WQM machine instruction.* The semantic is similar to amdgcn_strict_wwm with a notable difference that not all threads will be forcibly enabled during the computations of the intrinsic's argument, but only all threads in quads that have at least one thread active.* The difference between amdgc_wqm and amdgcn_strict_wqm, is that in the strict mode an inactive lane will always be enabled irrespective of control flow decisions.Reviewed By: critsonDifferential Revision: https://reviews.llvm.org/D96258 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Wed, 03 Mar 2021 09:18:28 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#c3ce7bae [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm * Introduce the new intrinsic amdgcn_strict_wwm * Deprecate the old intrinsic amdgcn_wwmThe change is done for consistency as the "strict"prefix will become an important, distinguishing factorbetween amdgcn_wqm and amdgcn_strictwqm in the future.The "strict" prefix indicates that inactive lanes do nottake part in control flow, specifically an inactive laneenabled by a strict mode will always be enabled irrespectiveof control flow decisions.The amdgcn_wwm will be removed, but doing so in two stepsgives users time to switch to the new name at their own pace.Reviewed By: critsonDifferential Revision: https://reviews.llvm.org/D96257 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Tue, 02 Mar 2021 08:38:07 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#560d7e04 [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets... to reduce headers dependency.Reviewed By: rampitec, arsenmDifferential Revision: https://reviews.llvm.org/D95036 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Wed, 20 Jan 2021 12:48:02 +0000 dfukalov <daniil.fukalov@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#6a87e9b0 [NFC][AMDGPU] Reduce include files dependency.Reviewed By: rampitecDifferential Revision: https://reviews.llvm.org/D93813 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Fri, 25 Dec 2020 15:52:14 +0000 dfukalov <daniil.fukalov@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#86b8f691 AMDGPU: Reorder checks List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Sat, 17 Oct 2020 18:28:52 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#43d34799 [NFC][MC] Use MCRegister in LiveRangeMatrixThe change starts from LiveRangeMatrix and also checks the users of theAPIs are typed accordingly.Differential Revision: https://reviews.llvm.org/D89145 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Fri, 09 Oct 2020 17:04:29 +0000 Mircea Trofin <mtrofin@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#34978602 [AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister... in favour of the isPhysical/isVirtual methods. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Thu, 20 Aug 2020 16:46:16 +0000 Jay Foad <jay.foad@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#05da2fe5 Sink all InitializePasses.h includesThis file lists every pass in LLVM, and is included by Pass.h, which isvery popular. Every time we add, remove, or rename a pass in LLVM, itcaused lots of recompilation.I found this fact by looking at this table, which is sorted by thenumber of times a file was changed over the last 100,000 git commitsmultiplied by the number of object files that depend on it in thecurrent checkout: recompiles touches affected_files header 342380 95 3604 llvm/include/llvm/ADT/STLExtras.h 314730 234 1345 llvm/include/llvm/InitializePasses.h 307036 118 2602 llvm/include/llvm/ADT/APInt.h 213049 59 3611 llvm/include/llvm/Support/MathExtras.h 170422 47 3626 llvm/include/llvm/Support/Compiler.h 162225 45 3605 llvm/include/llvm/ADT/Optional.h 158319 63 2513 llvm/include/llvm/ADT/Triple.h 140322 39 3598 llvm/include/llvm/ADT/StringRef.h 137647 59 2333 llvm/include/llvm/Support/Error.h 131619 73 1803 llvm/include/llvm/Support/FileSystem.hBefore this change, touching InitializePasses.h would cause 1345 filesto recompile. After this change, touching it only causes 550 compiles inan incremental rebuild.Reviewers: bkramer, asbirlea, bollu, jdoerfertDifferential Revision: https://reviews.llvm.org/D70211 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Wed, 13 Nov 2019 21:15:01 +0000 Reid Kleckner <rnk@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#0c476111 Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMSummary:This clang-tidy check is looking for unsigned integer variables whose initializerstarts with an implicit cast from llvm::Register and changes the type of thevariable to llvm::Register (dropping the llvm:: where possible).Partial reverts in:X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegisterX86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegisterX86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegisterHexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const RegisterPPCFastISel.cpp - No Register::operator-=()PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructorManual fixups in:ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/RegisterHexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&Depends on D65919Reviewers: arsenm, bogner, craig.topper, RKSimonReviewed By: arsenmSubscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D65962llvm-svn: 369041 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Thu, 15 Aug 2019 19:22:08 +0000 Daniel Sanders <daniel_l_sanders@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#2bea69bf Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFCllvm-svn: 367633 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Thu, 01 Aug 2019 23:27:28 +0000 Daniel Sanders <daniel_l_sanders@apple.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp#0a30f33c [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.This change incorporates an effort by Connor Abbot to change how we dealwith WWM operations potentially trashing valid values in inactive lanes.Previously, the SIFixWWMLiveness pass would work out which registerswere being trashed within WWM regions, and ensure that the registerallocator did not have any values it was depending on resident in thoseregisters if the WWM section would trash them. This worked perfectlywell, but would cause sometimes severe register pressure when the WWMsection resided before divergent control flow (or at least that is whereI mostly observed it).This fix instead runs through the WWM sections and pre allocates someregisters for WWM. It then reserves these registers so that the registerallocator cannot use them. This results in a significant registersaving on some WWM shaders I'm working with (130 -> 104 VGPRs, with justthis change!).Differential Revision: https://reviews.llvm.org/D59295llvm-svn: 357400 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp Mon, 01 Apr 2019 15:19:52 +0000 Neil Henning <neil.henning@amd.com>