Changes in LegalizeTypes.h

07d69d9f - [VP] Legalize the stride operand for EXPERIMENTAL_VP_STRIDED SDNodes

Wed, 20 Jul 2022 08:20:55 +0000

[VP] Legalize the stride operand for EXPERIMENTAL_VP_STRIDED SDNodesAdd promotion and expansion of integer operands forexperimental_vp_strided SelectionDAG nodes; the expansion is actuallyjust a truncation of the stride operand.Reviewed By: simollDifferential Revision: https://reviews.llvm.org/D123112 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

2e62a26f - [stackmaps] Legalise patchpoint arguments.

Fri, 15 Jul 2022 11:00:14 +0000

[stackmaps] Legalise patchpoint arguments.This is similar to D125680, but for llvm.experimental.patchpoint(instead of llvm.experimental.stackmap).Differential review: https://reviews.llvm.org/D129268 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

ed8ef65f - [stackmaps] Start legalizing live variable operands

Fri, 17 Jun 2022 12:20:03 +0000

[stackmaps] Start legalizing live variable operandsPrior to this change, live variable operands passed to`llvm.experimental.stackmap` would be emitted directly to target nodes,meaning that they don't get legalised. The upshot of this is that LLVMmay crash when encountering illegally typed target nodes.e.g. https://github.com/llvm/llvm-project/issues/21657This change introduces a platform independent stackmap DAG node whoseoperands are legalised as per usual, thus avoiding aforementionedcrashes.Note that some kinds of argument are still not handled properly, namelyvectors, structs, and large integers, like i128s. These will need to beaddressed in follow-up changes.Note also that this does not change the behaviour of`llvm.experimental.patchpoint`. A follow up change will do the same forthis intrinsic.Differential review:https://reviews.llvm.org/D125680 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

f2bcf330 - [LegalizeTypes][NFC] Merge promote SPLAT_VECTOR and promote SCALAR_TO_VECTOR to one function

Wed, 15 Jun 2022 03:46:57 +0000

[LegalizeTypes][NFC] Merge promote SPLAT_VECTOR and promote SCALAR_TO_VECTOR to one functionReviewed By: RKSimonDifferential Revision: https://reviews.llvm.org/D127825 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

00bfaba9 - [LegalizeTypes] Don't assume fshl/fshr shift amount type matches the other operands.

Fri, 06 May 2022 17:31:18 +0000

[LegalizeTypes] Don't assume fshl/fshr shift amount type matches the other operands.Like other shifts, the type isn't required to match. We shouldn'tassume we can call ZExtPromotedInteger.I tested the PromoteIntOp_FunnelShift locally by removing the promotionof the shift amount from PromoteIntRes_FunnelShift. But with the finalversion of this patch it is never executed on any tests.Differential Revision: https://reviews.llvm.org/D125106 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

170a9031 - Intrinsic for checking floating point class

Sun, 10 Oct 2021 15:46:58 +0000

Intrinsic for checking floating point classThis change introduces a new intrinsic, `llvm.is.fpclass`, which checksif the provided floating-point number belongs to any of the the specifiedvalue classes. The intrinsic implements the checks made by C standardlibrary functions `isnan`, `isinf`, `isfinite`, `isnormal`, `issubnormal`,`issignaling` and corresponding IEEE-754 operations.The primary motivation for this intrinsic is the support of strict FPmode. In this mode using compare instructions or other FP operations isnot possible, because if the value is a signaling NaN, floating-pointexception `Invalid` is raised, but the aforementioned functions mustnever raise exceptions.Currently there are two solutions for this problem, both areimplemented partially. One of them is using integer operations toimplement the check. It was implemented in https://reviews.llvm.org/D95948for `isnan`. It solves the problem of exceptions, but offers onesolution for all targets, although some can do the check in moreefficient way.The other, implemented in https://reviews.llvm.org/D96568, introduced ahook 'clang::TargetCodeGenInfo::testFPKind', which injects a targetspecific code into IR to implement `isnan` and some other functions. It isconvenient for targets that have dedicated instruction to determine FP dataclass. However using target-specific intrinsic complicates analysis and canprevent some optimizations.A special intrinsic for value class checks allows representing data classtests with enough flexibility. During IR transformations it represents thecheck in target-independent way and saves it from undesired transformations.In the instruction selector it allows efficient lowering depending on theused target and mode.This implementation is an extended variant of `llvm.isnan` introducedin https://reviews.llvm.org/D104854. It is limited to minimal intrinsicsupport. Target-specific treatment will be implemented in separatepatches.Differential Revision: https://reviews.llvm.org/D112025 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

ed98c1b3 - Cleanup includes: DebugInfo & CodeGen

Wed, 09 Mar 2022 21:29:31 +0000

Cleanup includes: DebugInfo & CodeGenDiscourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanupDifferential Revision: https://reviews.llvm.org/D121332 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

2233befa - [LegalizeTypes][VP] Add splitting support for vp.gather and vp.scatter

Tue, 25 Jan 2022 10:05:50 +0000

[LegalizeTypes][VP] Add splitting support for vp.gather and vp.scatterSplit these nodes in a similar way as their masked versions.Reviewed By: frasercrmck, craig.topperDifferential Revision: https://reviews.llvm.org/D117760 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

c10c7488 - [LegalizeTypes][VP] Add widening support for vp.gather and vp.scatter

Thu, 20 Jan 2022 08:13:00 +0000

[LegalizeTypes][VP] Add widening support for vp.gather and vp.scatterReviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117557 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

b7bf96a2 - [LegalizeTypes][VP] Add widening support for vp.reduce.*

Tue, 18 Jan 2022 09:30:31 +0000

[LegalizeTypes][VP] Add widening support for vp.reduce.*When widening these intrinsics, we do not have to insert neutralelements at the end of the vector as when widening vector.reduce.*intrinsics, thanks to vector predication semantics.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117467 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

fd1dce35 - [LegalizeTypes][VP] Add splitting support for vp.reduction.*

Mon, 17 Jan 2022 15:55:18 +0000

[LegalizeTypes][VP] Add splitting support for vp.reduction.*Split vp.reduction.* intrinsics by splitting the vector to reduce intwo halves, perform the reduction operation in each one of them andaccumulate the results of both operations.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117469 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

f4515ab8 - Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

Tue, 18 Jan 2022 08:40:01 +0000

Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"This reverts commit 197f3c0deb76951315118ef13937b67ea9cbd5aa.Reverting after miscompilation errors discovered with ffmpeg. List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

197f3c0d - [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

Mon, 22 Nov 2021 11:38:06 +0000

[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constantsWhen we know the value we're extending is a negative constant then itmakes sense to use SIGN_EXTEND because this may improve code quality insome cases, particularly when doing a constant splat of an unpacked vectortype. For example, for SVE when splatting the value -1 into all elementsof a vector of type the element type will get promotedfrom i32 -> i64. In this case we want the splat value to sign-extend from(i32 -1) -> (i64 -1), whereas currently it zero-extends from(i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can usea single mov immediate instruction.New tests added here: CodeGen/AArch64/sve-vector-splat.llI believe we see some code quality improvements in these existingtests too: CodeGen/AArch64/reduce-and.ll CodeGen/AArch64/unfold-masked-merge-vector-variablemask.llThe apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll onlyoccur because the test disables codegen prepare and branch folding.Differential Revision: https://reviews.llvm.org/D114357 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

877d1b3d - [SelectionDAG][VP] Add splitting/widening for VP_LOAD and VP_STORE

Thu, 13 Jan 2022 17:23:07 +0000

[SelectionDAG][VP] Add splitting/widening for VP_LOAD and VP_STOREOriginal patch by @hussainjk.This patch was split off from D109377 to keep vector legalization(widening/splitting) separate from vector element legalization(promoting).While the original patch added a third overload ofSelectionDAG::getVPStore, this patch takes the liberty of collapsingthose all down to 1, as three overloads seems excessive for alittle-used node.The original patch also used ModifyToType in places, but that methodstill crashes on scalable vector types. Seeing as the other VPlegalization methods only work when all operands need identicalwidening, this patch follows in that vein.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117235 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

ba471ba8 - Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

Thu, 13 Jan 2022 15:59:03 +0000

Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"This reverts commit 31009f0b5afb504fc1f30769c038e1b7be6ea45b.It seems to be causing SVE VLA buildbot failures and has introduced agenuine regression. Reverting for now. List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

31009f0b - [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

Mon, 22 Nov 2021 11:38:06 +0000

[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constantsWhen we know the value we're extending is a negative constant then itmakes sense to use SIGN_EXTEND because this may improve code quality insome cases, particularly when doing a constant splat of an unpacked vectortype. For example, for SVE when splatting the value -1 into all elementsof a vector of type the element type will get promotedfrom i32 -> i64. In this case we want the splat value to sign-extend from(i32 -1) -> (i64 -1), whereas currently it zero-extends from(i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can usea single mov immediate instruction.New tests added here: CodeGen/AArch64/sve-vector-splat.llI believe we see some code quality improvements in these existingtests too: CodeGen/AArch64/dag-numsignbits.ll CodeGen/AArch64/reduce-and.ll CodeGen/AArch64/unfold-masked-merge-vector-variablemask.llThe apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll onlyoccur because the test disables codegen prepare and branch folding.Differential Revision: https://reviews.llvm.org/D114357 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

38efa68b - [LegalizeTypes][VP] Add splitting support for vp.select

Fri, 07 Jan 2022 07:54:08 +0000

[LegalizeTypes][VP] Add splitting support for vp.selectSplit vp.select in a similar way as vselect, splitting also the lengthparameter.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D116651 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

88ecdd30 - [LegalizeTypes] Remove IsVP argument from type legalization methods. NFC

Wed, 05 Jan 2022 16:52:53 +0000

[LegalizeTypes] Remove IsVP argument from type legalization methods. NFCWe can either check the opcode or number of operands or useISD::isVPOpcode inside the methods.In some places I've used number of operands figuring that it ischeaper than isVPOpcode. I've included isVPOpcode in an assert toverify.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D116578 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

96e220e6 - [LegalizeTypes][VP] Add integer promotion support for vp.select

Wed, 05 Jan 2022 09:23:31 +0000

[LegalizeTypes][VP] Add integer promotion support for vp.selectPromote select, vselect and vp.select in a similar way.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D116400 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

df5226df - [LegalizeTypes][VP] Add widening support for vp.select

Wed, 05 Jan 2022 08:07:46 +0000

[LegalizeTypes][VP] Add widening support for vp.selectWiden vp.select the same way as select and vselect.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D116407 List of files: /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h