Changes in FormatTestVerilog.cpp en Copyright 2015 Java 2e32ff10 - [clang-format] Handle Verilog preprocessor directives http://172.16.0.5:8080/history/llvm-project-15.0.7/clang/unittests/Format/FormatTestVerilog.cpp#2e32ff10 [clang-format] Handle Verilog preprocessor directivesVerilog uses the backtick instead of the hash. In this revisionbackticks are lexed manually and then get labeled as hashes so the logicfor handling C preprocessor stuff don't have to change. Hashes getlabeled as identifiers for Verilog-specific stuff like delays.Reviewed By: HazardyKnusperkeksDifferential Revision: https://reviews.llvm.org/D124749 List of files: /llvm-project-15.0.7/clang/unittests/Format/FormatTestVerilog.cpp Sun, 26 Jun 2022 01:54:02 +0000 sstwcw <f0gukp2nk@protonmail.com> 9ed2e68c - [clang-format] Parse Verilog if statements http://172.16.0.5:8080/history/llvm-project-15.0.7/clang/unittests/Format/FormatTestVerilog.cpp#9ed2e68c [clang-format] Parse Verilog if statementsThis patch mainly handles treating `begin` as block openers.While and for statements will be handled in another patch.Reviewed By: HazardyKnusperkeksDifferential Revision: https://reviews.llvm.org/D123450 List of files: /llvm-project-15.0.7/clang/unittests/Format/FormatTestVerilog.cpp Sun, 26 Jun 2022 01:51:40 +0000 sstwcw <f0gukp2nk@protonmail.com>