Changes in attr-arm-sve-vector-bits.cpp

0ce46a1d - [AArch64][Driver][SVE] Allow -msve-vector-bits=+ syntax to mean no maximum vscale

Thu, 14 Oct 2021 11:04:33 +0000

[AArch64][Driver][SVE] Allow -msve-vector-bits=+ syntax to mean no maximum vscaleThis patch splits the existing SveVectorBits LangOpt into VScaleMin andVScaleMax LangOpts such that we can represent such an option. The cc1option has also been split into -mvscale-{min,max}= options so that thecc1 arguments better reflect the vscale_range IR attribute.Differential Revision: https://reviews.llvm.org/D111790 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

599b2f00 - [AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion

Mon, 19 Jul 2021 13:10:17 +0000

[AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversionAccording to https://godbolt.org/z/q5rME1naY and acle, we found thatthere are different SVE conversion behaviours between clang and gcc. It turnsout that llvm does not handle SVE predicates width properly.This patch 1) checks SVE predicates width rightly with svbool_t type.2) removes warning on svbool_t VLST <-> VLAT/GNUT conversion.3) disables VLST <-> VLAT/GNUT conversion between SVE vectors and predicatesdue to different width.Differential Revision: https://reviews.llvm.org/D106333 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

1b1b30cf - [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

Fri, 19 Feb 2021 17:09:50 +0000

[clang][SVE] Don't warn on vector to sizeless builtin implicit conversionThis commit prevents warnings from -Wconversion when a clang vector typeis implicitly converted to a sizeless builtin type -- for example, whenimplicitly converting a fixed-predicate to a scalable predicate.The code below: 1 #include 2 3 #define N __ARM_FEATURE_SVE_BITS 4 #define FIXED_ATTR __attribute__((arm_sve_vector_bits (N))) 5 typedef svbool_t fixed_svbool_t FIXED_ATTR; 6 7 inline fixed_svbool_t foo(fixed_svbool_t p) { 8 return svnot_z(svptrue_b64(), p); 9 }would previously raise this warning: warning: implicit conversion turns vector to scalar: \ 'fixed_svbool_t' (vector of 8 'unsigned char' values) to 'svbool_t' \ (aka '__SVBool_t') [-Wconversion]Note that many cases of these implicit conversions were alreadypermitted because many functions inside arm_sve.h are spawned viapreprocessor macros, and the call to isInSystemMacro would cover us inthis case. This commit fixes the remaining cases.Differential Revision: https://reviews.llvm.org/D97053 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

9218f928 - [clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors

Fri, 11 Sep 2020 15:18:44 +0000

[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectorsThis patch adds support for implicit casting between GNU vectors and SVEvectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm CLanguage Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1].This behavior makes it possible to use GNU vectors with ACLE functionsthat operate on VLAT. For example: typedef int8_t vec __attribute__((vector_size(32))); vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); }Tests are also added for implicit casting between GNU and fixed-lengthSVE vectors created by the 'arm_sve_vector_bits' attribute. Thisbehavior makes it possible to use VLST with existing interfaces thatoperate on GNUT. For example: typedef int8_t vec1 __attribute__((vector_size(32))); void f(vec1); #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); void g(vec2 x) { f(x); } // OK #endifThe `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicatesinteroperability with the GNU vector extension. This is the first patchproviding support for this feature, which once complete will be enabledby the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` featurecurrently is.[1] https://developer.arm.com/documentation/100987/latestReviewed By: efriedmaDifferential Revision: https://reviews.llvm.org/D87607 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

f9091e56 - [clang][aarch64] Drop experimental from __ARM_FEATURE_SVE_BITS macro

Thu, 03 Sep 2020 09:19:41 +0000

[clang][aarch64] Drop experimental from __ARM_FEATURE_SVE_BITS macroThe __ARM_FEATURE_SVE_BITS feature macro is specified in the Arm CLanguage Extensions (ACLE) for SVE [1] (version 00bet5). From the spec,where __ARM_FEATURE_SVE_BITS==N: When N is nonzero, indicates that the implementation is generating code for an N-bit SVE target and that the arm_sve_vector_bits(N) attribute is available.This was defined in D83550 as __ARM_FEATURE_SVE_BITS_EXPERIMENTAL andenabled under the -msve-vector-bits flag to simplify initial tests.This patch drops _EXPERIMENTAL now there is support for the feature.[1] https://developer.arm.com/documentation/100987/latestReviewed By: david-armDifferential Revision: https://reviews.llvm.org/D86720 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

feed5a72 - [Sema][AArch64] Support arm_sve_vector_bits attribute

Tue, 11 Aug 2020 13:04:21 +0000

[Sema][AArch64] Support arm_sve_vector_bits attributeThis patch implements the semantics for the 'arm_sve_vector_bits' typeattribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].The purpose of this attribute is to define vector-length-specific (VLS)versions of existing vector-length-agnostic (VLA) types.The semantics were already implemented by D83551, although theimplementation approach has since changed to represent VLSTs asVectorType in the AST and fixed-length vectors in the IR everywhereexcept in function args/returns. This is described in the prototypepatch D85128 demonstrating the new approach.The semantic changes added in D83551 are changed since theAttributedType is replaced by VectorType in the AST. Minimal changeswere necessary in the previous patch as the canonical type for both VLAand VLS was the same (i.e. sizeless), except in constructs such asglobals and structs where sizeless types are unsupported. This patchreverts the changes that permitted VLS types that were represented assizeless types in such circumstances, and adds support for implicitcasting between VLA <-> VLS types as described in section 3.7.3.2 of theACLE.Since the SVE builtin types for bool and uint8 are both represented asBuiltinType::UChar in VLSTs, two new vector kinds are implemented todistinguish predicate and data vectors.[1] https://developer.arm.com/documentation/100987/latestReviewed By: aaron.ballmanDifferential Revision: https://reviews.llvm.org/D85736 List of files: /llvm-project-15.0.7/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp