Changes in .gitignore

f889a2e8 - selftests/powerpc: Add missing PMU selftests to .gitignores

Fri, 12 Aug 2022 07:16:32 +0000

selftests/powerpc: Add missing PMU selftests to .gitignoresSome recently added selftests don't have their binaries in .gitignores,so add them.I also alphabetically sorted sampling_tests/.gitignore while I was inthere.Signed-off-by: Russell Currey Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220812071632.56095-1-ruscur@russell.cc List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

29cf373c - selftests/powerpc/pmu: Add interface test for mmcra register fields

Thu, 27 Jan 2022 07:20:12 +0000

selftests/powerpc/pmu: Add interface test for mmcra register fieldsThe testcase uses event code 0x35340401e0 to verify the settings fordifferent fields in Monitor Mode Control Register A (MMCRA). The fieldsinclude thresh_start, thresh_stop thresh_select, sdar mode, sample andmarked bit. Checks if these fields are translated correctly via perfinterface to MMCRA.Signed-off-by: Kajol Jain [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-21-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

02f02feb - selftests/powerpc/pmu/: Add interface test for mmcr3_src fields

Thu, 27 Jan 2022 07:20:11 +0000

selftests/powerpc/pmu/: Add interface test for mmcr3_src fieldsThe testcase uses event code 0x1340000001c040 to verify the settings fordifferent src fields in Monitor Mode Control Register 3 (MMCR3). Checksif these fields are translated correctly via perf interface to MMCR3 onISA v3.1 platform.Signed-off-by: Kajol Jain [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-20-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

9ee241f1 - selftests/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields

Thu, 27 Jan 2022 07:20:10 +0000

selftests/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fieldsThe testcases uses cycles event to verify the freeze counter settings inMonitor Mode Control Register 2 (MMCR2). Event modifier (exclude_kernel)setting is used for the event attribute to check the FCxS and FCxH (Freeze counter in privileged and hypervisor state ) settings via perfinterface.Signed-off-by: Madhavan Srinivasan [mpe: Add error checking, check MSR for MSR_HV, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-19-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

ac575b26 - selftests/powerpc/pmu/: Add interface test for mmcr2_l2l3 field

Thu, 27 Jan 2022 07:20:09 +0000

selftests/powerpc/pmu/: Add interface test for mmcr2_l2l3 fieldThe testcases uses event code 0x010000046080 to verify the l2l3 bitsetting for Monitor Mode Control Register 2 (MMCR2). check if this bitis set correctly via perf interface in ISA v3.1 platform.Signed-off-by: Madhavan Srinivasan [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-18-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

2becea3b - selftests/powerpc/pmu/: Add interface test for mmcr1_comb field

Thu, 27 Jan 2022 07:20:07 +0000

selftests/powerpc/pmu/: Add interface test for mmcr1_comb fieldThe testcase uses event code "0x26880" to verify the settings fordifferent fields in Monitor Mode Control Register 1 (MMCR1). The fieldinclude PMCxCOMB. Checks if this field are translated correctly via perfinterface to MMCR1Add selftest for mmcr1 comb field.Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-16-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

6e11374b - selftests/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5

Thu, 27 Jan 2022 07:20:06 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5The testcase uses event code 0x500fa to verify the FC5-6 bit setting inMonitor Mode Control Register 0 (MMCR0). Check if FC5-6 bit is not setin MMCR0 when using Performance Monitor Counter 5 and 6 (PMC5 and PMC6).Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-15-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

d5172f25 - selftests/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1

Thu, 27 Jan 2022 07:20:05 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1The testcase uses event code 0x1001e to verify two bit settings (FC5-6and PMC1CE) in Monitor Mode Control Register 0 (MMCR0). Check if FC5-6bit to be set in MMCR0 when not using Performance Monitor Counter 5 and6 (PMC5 and PMC6). And also PMC1CE is expected to be set when usingPMC1. Test if these fields are programmed correctly via perf interface.Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-14-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

9ac7c6d5 - selftests/powerpc/pmu/: Add interface test for mmcr0_pmcjce field

Thu, 27 Jan 2022 07:20:04 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0_pmcjce fieldThe testcase uses event code 0x500fa ("instructions") to verify thePMCjCE bit setting in Monitor Mode Control Register 0 (MMCR0). This bitis expected to be set in MMCR0 when using Performance Monitor Counter5 (PMC5). Checks if perf interface sets this bit correctly.Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-13-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

b24142b9 - selftests/powerpc/pmu/: Add interface test for mmcr0_pmccext bit

Thu, 27 Jan 2022 07:20:03 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0_pmccext bitThe testcase uses cycles event to check the PMCCEXT bit setting inMonitor Mode Control Register 0 (MMCR0). Check if perf interface setsthis control bit in MMCR0 on ISA v3.1 platform.Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-12-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

a7c0ab2e - selftests/powerpc/pmu/: Add interface test for mmcr0_cc56run field

Thu, 27 Jan 2022 07:20:02 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0_cc56run fieldThe testcase uses event code 0x500fa ("instructions") to check theCC56RUN bit setting in Monitor Mode Control Register 0(MMCR0). In ISAv3.1 platform, this bit is expected to be set in MMCR0 when usingPerformance Monitor Counter 5 and 6 (PMC5 and PMC6). Verify this is donecorrectly by perf interface.CC56RUN bit makes PMC5 and PMC6 count regardless of the run latch state.This bit is set in power10 since PMC5 and PMC6 is used in power10 forcounting instructions and cycles. Hence added a check to skip this testin other platformsSigned-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-11-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore

eb7aa044 - selftests/powerpc/pmu/: Add interface test for mmcr0 exception bits

Thu, 27 Jan 2022 07:20:01 +0000

selftests/powerpc/pmu/: Add interface test for mmcr0 exception bitsThe testcase uses "instructions" event to verify two bits(PMAE and PMAO)in Monitor Mode Control Register 0 (MMCR0). At the time of interrupt,pmae bit ( which enables performance monitor exception ) is expected tobe cleared and pmao (which indicates performance monitor alert) bit isexpected to be set in MMCR0. And testcases handles these checks.Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-10-kjain@linux.ibm.com List of files: /linux-6.15/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore