Changes in Kbuild

36f257e3 - acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors

Mon, 10 Mar 2025 22:38:38 +0000

acpi/ghes, cxl/pci: Process CXL CPER Protocol ErrorsWhen PCIe AER is in FW-First, OS should process CXL Protocol errors fromCPER records. Introduce support for handling and logging CXL Protocolerrors.The defined trace events cxl_aer_uncorrectable_error andcxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse themto trace FW-First Protocol errors.Since the CXL code is required to be called from process context andGHES is in interrupt context, use workqueues for processing.Similar to CXL CPER event handling, use kfifo to handle errors as itsimplifies queue processing by providing lock free fifo operations.Add the ability for the CXL sub-system to register a workqueue toprocess CXL CPER protocol errors.[DJ: return cxl_cper_register_prot_err_work() directly in cxl_ras_init()]Signed-off-by: Smita Koralahalli Reviewed-by: Li Ming Reviewed-by: Alison Schofield Reviewed-by: Ira Weiny Reviewed-by: Tony Luck Link: https://patch.msgid.link/20250310223839.31342-2-Smita.KoralahalliChannabasappa@amd.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

516e5bd0 - cxl: Add mce notifier to emit aliased address for extended linear cache

Wed, 26 Feb 2025 16:21:21 +0000

cxl: Add mce notifier to emit aliased address for extended linear cacheBelow is a setup with extended linear cache configuration with an examplelayout of memory region shown below presented as a single memory regionconsists of 256G memory where there's 128G of DRAM and 128G of CXL memory.The kernel sees a region of total 256G of system memory. 128G DRAM 128G CXL memory|-----------------------------------|-------------------------------------|Data resides in either DRAM or far memory (FM) with no replication. Hotdata is swapped into DRAM by the hardware behind the scenes. When error isdetected in one location, it is possible that error also resides in thealiased location. Therefore when a memory location that is flagged by MCEis part of the special region, the aliased memory location needs to beofflined as well.Add an mce notify callback to identify if the MCE address location is partof an extended linear cache region and handle accordingly.Added symbol export to set_mce_nospec() in x86 code in order to callset_mce_nospec() from the CXL MCE notify callback.Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20250226162224.3633792-5-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

0ec9849b - acpi/hmat / cxl: Add extended linear cache support for CXL

Wed, 26 Feb 2025 16:21:19 +0000

acpi/hmat / cxl: Add extended linear cache support for CXLThe current cxl region size only indicates the size of the CXL memoryregion without accounting for the extended linear cache size. Retrieve thecache size from HMAT and append that to the cxl region size for the cxlregion range that matches the SRAT range that has extended linear cacheenabled.The SRAT defines the whole memory range that includes the extended linearcache and the CXL memory region. The new HMAT ECN/ECR to the Memory SideCache Information Structure defines the size of the extended linear cachesize and matches to the SRAT Memory Affinity Structure by the memoryproxmity domain. Add a helper to match the cxl range to the SRAT memoryrange in order to retrieve the cache size.There are several places that checks the cxl region range against thedecoder range. Use new helper to check between the two ranges and addressthe new cache size.Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20250226162224.3633792-3-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

f0e6a232 - cxl: Add Get Supported Features command for kernel usage

Thu, 20 Feb 2025 19:42:40 +0000

cxl: Add Get Supported Features command for kernel usageCXL spec r3.2 8.2.9.6.1 Get Supported Features (Opcode 0500h)The command retrieve the list of supported device-specific features(identified by UUID) and general information about each Feature.The driver will retrieve the Feature entries in order to make checks andprovide information for the Get Feature and Set Feature command. One ofthe main piece of information retrieved are the effects a Set Featurecommand would have for a particular feature. The retrieved Featureentries are stored in the cxl_mailbox context.The setup of Features is initiated via devm_cxl_setup_features() during thepci probe function before the cxl_memdev is enumerated.Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Reviewed-by: Li Ming Reviewed-by: Davidlohr Bueso Tested-by: Shiju Jose Link: https://patch.msgid.link/20250220194438.2281088-3-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

577a6766 - cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()

Fri, 30 Aug 2024 06:13:06 +0000

cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()The name of cxl_setup_parent_dport() function is not clear, the functionis used to initialize AER and RAS capabilities on a dport, therefore,rename the function to cxl_dport_init_ras_reporting(), it is easier foruser to understand what the function does. Besides, adjust the order ofthe function parameters, the subject of cxl_dport_init_ras_reporting()is a cxl dport, so a struct cxl_dport as the first parameter of thefunction should be better.cxl_dport_map_regs() is used to map CXL RAS capability on a cxl dport,using cxl_dport_map_ras() as the function name.Signed-off-by: Li Ming Reviewed-by: Jonathan Cameron Link: https://patch.msgid.link/20240830061308.2327065-1-ming4.li@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

2c402bd2 - cxl/test: Skip cxl_setup_parent_dport() for emulated dports

Fri, 09 Aug 2024 08:27:50 +0000

cxl/test: Skip cxl_setup_parent_dport() for emulated dportsThe cxl_test unit test environment on qemu always hits below call tracewith KASAN enabled: BUG: KASAN: slab-out-of-bounds in cxl_setup_parent_dport+0x480/0x530 [cxl_core] Read of size 1 at addr ff110000676014f8 by task (udev-worker)/676[ 24.424403] CPU: 2 PID: 676 Comm: (udev-worker) Tainted: G O N 6.10.0-qemucxl #1 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240214-2.el9 02/14/2024 Call Trace: dump_stack_lvl+0xea/0x150 print_report+0xce/0x610 ? kasan_complete_mode_report_info+0x40/0x200 kasan_report+0xcc/0x110 __asan_report_load1_noabort+0x18/0x20 cxl_setup_parent_dport+0x480/0x530 [cxl_core] cxl_mem_probe+0x49b/0xaa0 [cxl_mem]cxl_test module models a CXL topology for testing, it creates someemulated dports with platform devices in the CXL topology, so thedport_dev of an emulated dport points to a platform device rather than apci device or a pci host bridge in the case. Currently,cxl_setup_parent_dport() is used to set up RAS and AER capability on thedport connected to the CXL memory device, but cxl_test does not supportRAS or AER functionality yet, so the fix is implementing a__wrap_cxl_setup_parent_dport() to filter out all emulated dports,guarantees only real dports can be handled by cxl_setup_parent_dport().Fixes: f05fd10d138d ("cxl/pci: Add RCH downstream port AER register discovery")Reported-by: Pengfei Xu Closes: https://lore.kernel.org/linux-cxl/ZrHTBp2O+HtUe6kt@xpf.sh.intel.com/T/#tSigned-off-by: Li Ming Reviewed-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Alison Schofield Tested-by: Ira Weiny Tested-by: Alison Schofield Link: https://patch.msgid.link/20240809082750.3015641-3-ming4.li@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/tools/testing/cxl/Kbuild

117132ed - cxl/test: Add support for qos_class checking

Tue, 06 Feb 2024 19:03:40 +0000

cxl/test: Add support for qos_class checkingSet a fake qos_class to a unique value in order to do simple testing ofqos_class for root decoders and mem devs via user cxl_test. A mockfunction is added to set the fake qos_class values for memory deviceand overrides cxl_endpoint_parse_cdat() in cxl driver code.Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/20240206190431.1810289-5-dave.jiang@intel.comReviewed-by: Jonathan Cameron Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

68deb997 - tools/testing/cxl: Disable "missing prototypes / declarations" warnings

Tue, 16 Jan 2024 21:17:17 +0000

tools/testing/cxl: Disable "missing prototypes / declarations" warningsPrevent warnings of the form:tools/testing/cxl/test/mock.c:44:6: error: no previous prototype for‘__wrap_is_acpi_device_node’ [-Werror=missing-prototypes]tools/testing/cxl/test/mock.c:63:5: error: no previous prototype for‘__wrap_acpi_table_parse_cedt’ [-Werror=missing-prototypes]tools/testing/cxl/test/mock.c:81:13: error: no previous prototype for‘__wrap_acpi_evaluate_integer’ [-Werror=missing-prototypes]...by locally disabling some warnings.It turns out that:Commit 0fcb70851fbf ("Makefile.extrawarn: turn on missing-prototypes globally")...in addition to expanding in-tree coverage, also impacts out-of-treemodule builds like those in tools/testing/cxl/.Filter out the warning options on unit test code that does not effectmainline builds.Reviewed-by: Alison Schofield Link: https://lore.kernel.org/r/170543983780.460832.10920261849128601697.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

ad6f04c0 - cxl: Add callback to parse the DSMAS subtables from CDAT

Thu, 21 Dec 2023 22:03:13 +0000

cxl: Add callback to parse the DSMAS subtables from CDATProvide a callback function to the CDAT parser in order to parse theDevice Scoped Memory Affinity Structure (DSMAS). Each DSMAS structurecontains the DPA range and its associated attributes in each entry. Seethe CDAT specification for details. The device handle and the DPA rangeis saved and to be associated with the DSLBIS locality data when theDSLBIS entries are parsed. The xarray is a local variable. When thetotal path performance data is calculated and storred this xarray can bediscarded.Coherent Device Attribute Table 1.03 2.1 Device Scoped memory AffinityStructure (DSMAS)Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/170319619355.2212653.2675953129671561293.stgit@djiang5-mobl3Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

e05501e8 - cxl: Add cxl_num_decoders_committed() usage to cxl_test

Mon, 06 Nov 2023 17:26:45 +0000

cxl: Add cxl_num_decoders_committed() usage to cxl_testCommit 458ba8189cb4 ("cxl: Add cxl_decoders_committed() helper") missed theconversion for cxl_test. Add usage of cxl_num_decoders_committed() toreplace the open coding.Suggested-by: Alison Schofield Signed-off-by: Dave Jiang Reviewed-by: Fan Ni Link: https://lore.kernel.org/r/169929160525.824083.11813222229025394254.stgit@djiang5-mobl3Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

8f0220af - Revert "cxl/port: Enable the HDM decoder capability for switch ports"

Thu, 15 Jun 2023 19:53:40 +0000

Revert "cxl/port: Enable the HDM decoder capability for switch ports"commit eb0764b822b9 ("cxl/port: Enable the HDM decoder capability for switch ports")...was added on the observation of CXL memory not being accessible aftersetting up a region on a "cold-plugged" device. A "cold-plugged" CXLdevice is one that was not present at boot, so platform-firmware/BIOShas no chance to set it up.While it is true that the debug found the enable bit clear in thehost-bridge's instance of the global control register (CXL 3.08.2.4.19.2 CXL HDM Decoder Global Control Register), that bit isdescribed as:"This bit is only applicable to CXL.mem devices and shallreturn 0 on CXL Host Bridges and Upstream Switch Ports."So it is meant to be zero, and further testing confirmed that this "fix"had no effect on the failure. Revert it, and be more vigilant aboutproposed fixes in the future. Since the original copied stable@, flagthis revert for stable@ as well.Cc: Fixes: eb0764b822b9 ("cxl/port: Enable the HDM decoder capability for switch ports")Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Link: https://lore.kernel.org/r/168685882012.3475336.16733084892658264991.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

eb4663b0 - cxl/acpi: Probe RCRB later during RCH downstream port creation

Sun, 25 Jun 2023 18:35:20 +0000

cxl/acpi: Probe RCRB later during RCH downstream port creationThe RCRB is extracted already during ACPI CEDT table parsing while thedata of this is needed not earlier than dport creation. Thisimplementation comes with drawbacks: During ACPI table scan there isalready MMIO access including mapping and unmapping, but only ACPIdata should be collected here. The collected data must be transferredthrough a couple of interfaces until it is finally consumed whencreating the dport. This causes complex data structures and functioninterfaces. Additionally, RCRB parsing will be extended to alsoextract AER data, it would be much easier do this at a later pointduring port and dport creation when the data structures are availableto hold that data.To simplify all that, probe the RCRB at a later point during RCHdownstream port creation. Change ACPI table parser to only extract thebase address of either the component registers or the RCRB. Parse andextract the RCRB in devm_cxl_add_rch_dport().This is in preparation to centralize all RCRB scanning.Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230622205523.85375-2-terry.bowman@amd.comCo-developed-by: Dan Williams Link: https://lore.kernel.org/r/20230622205523.85375-3-terry.bowman@amd.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

1ad3f701 - cxl/pci: Find and register CXL PMU devices

Fri, 26 May 2023 09:58:22 +0000

cxl/pci: Find and register CXL PMU devicesCXL PMU devices can be found from entries in the RegisterLocator DVSEC.Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230526095824.16336-4-Jonathan.Cameron@huawei.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

eb0764b8 - cxl/port: Enable the HDM decoder capability for switch ports

Thu, 18 May 2023 03:19:43 +0000

cxl/port: Enable the HDM decoder capability for switch portsDerick noticed, when testing hot plug, that hot-add behaves nominallyafter a removal. However, if the hot-add is done without a priorremoval, CXL.mem accesses fail. It turns out that the originalimplementation of the port driver and region programming wrongly assumedthat platform-firmware always enables the host-bridge HDM decodercapability. Add support turning on switch-level HDM decoders in the casewhere platform-firmware has not.The implementation is careful to only arrange for the enable to beundone if the current instance of the driver was the one that did theenable. This is to interoperate with platform-firmware that may expectCXL.mem to remain active after the driver is shutdown. This comes at thecost of potentially not shutting down the enable on kexec flows, but itis mitigated by the fact that the related HDM decoders still need to beenabled on an individual basis.Cc: Reported-by: Derick Marks Fixes: 54cdbf845cf7 ("cxl/port: Add a driver for 'struct cxl_port' objects")Reviewed-by: Ira Weiny Link: https://lore.kernel.org/r/168437998331.403037.15719879757678389217.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

59c3368b - cxl/port: Export cxl_dvsec_rr_decode() to cxl_port

Tue, 14 Feb 2023 19:41:13 +0000

cxl/port: Export cxl_dvsec_rr_decode() to cxl_portCall cxl_dvsec_rr_decode() in the beginning of cxl_port_probe() andpreserve the decoded information in a local'struct cxl_endpoint_dvsec_info'. This info can be passed to variousfunctions later on in order to support the HDM decoder emulation.The invocation of cxl_dvsec_rr_decode() in cxl_hdm_decode_init() isremoved and a pointer to the 'struct cxl_endpoint_dvsec_info' is passedin.Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/167640367377.935665.2848747799651019676.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

8c149eb0 - tools/testing/cxl: Prevent cxl_test from confusing production modules

Tue, 13 Dec 2022 16:44:24 +0000

tools/testing/cxl: Prevent cxl_test from confusing production modulesThe cxl_test machinery builds modified versions of the modules indrivers/cxl/ and intercepts some of their calls to allow cxl_test toinject mock CXL topologies for test.However, if cxl_test attempts the same with production modules,fireworks ensue as Luis discovered [1]. Prevent that scenario byarranging for cxl_test to check for a "watermark" symbol in each of themodules it expects to be modified before the test can run. This turnsundefined runtime behavior or crashes into a safer failure to load thecxl_test module.Link: http://lore.kernel.org/r/20221209062919.1096779-1-mcgrof@kernel.org [1]Reported-by: Luis Chamberlain Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

4a20bc3e - cxl/pci: Move tracepoint definitions to drivers/cxl/core/

Thu, 08 Dec 2022 17:02:00 +0000

cxl/pci: Move tracepoint definitions to drivers/cxl/core/CXL is using tracepoints for reporting RAS capability register payloadsfor AER events, and has plans to use tracepoints for the output payloadof Get Poison List and Get Event Records commands. For organizationpurposes it would be nice to keep those all under a single + local CXLtrace system. This also organization also potentially helps in thefuture when CXL drivers expand beyond generic memory expanders, howeverthat would also entail a move away from the expander-specificcxl_dev_state context, save that for later.Note that the powerpc-specific drivers/misc/cxl/ also defines a 'cxl'trace system, however, it is unlikely that a single platform will everload both drivers simultaneously.Cc: Steven Rostedt Tested-by: Alison Schofield Reviewed-by: Dave Jiang Link: https://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

d5b1a271 - cxl/acpi: Extract component registers of restricted hosts from RCRB

Sat, 03 Dec 2022 08:40:29 +0000

cxl/acpi: Extract component registers of restricted hosts from RCRBA downstream port must be connected to a component register block.For restricted hosts the base address is determined from the RCRB. TheRCRB is provided by the host's CEDT CHBS entry. Rework CEDT parser toget the RCRB and add code to extract the component register block fromit.RCRB's BAR[0..1] point to the component block containing CXL subsystemcomponent registers. MEMBAR extraction follows the PCI base spec here,esp. 64 bit extraction and memory range alignment (6.0, 7.5.1.2.1). TheRCRB base address is cached in the cxl_dport per-host bridge so that theupstream port component registers can be retrieved later by an RCD(RCIEP) associated with the host bridge.Note: Right now the component register block is used for HDM decodercapability only which is optional for RCDs. If unsupported by the RCD,the HDM init will fail. It is future work to bypass it in this case.Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Link: https://lore.kernel.org/r/Y4dsGZ24aJlxSfI1@rric.localdomain[djbw: introduce devm_cxl_add_rch_dport()]Link: https://lore.kernel.org/r/166993044524.1882361.2539922887413208807.stgit@dwillia2-xfh.jf.intel.comReviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

32828115 - cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation

Wed, 30 Nov 2022 19:21:36 +0000

cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationAdd nvdimm_security_ops support for CXL memory device with the introductionof the ->get_flags() callback function. This is part of the "PersistentMemory Data-at-rest Security" command set for CXL memory device support.The ->get_flags() function provides the security state of the persistentmemory device defined by the CXL 3.0 spec section 8.2.9.8.6.1.Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/166983609611.2734609.13231854299523325319.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild

779dd20c - cxl/region: Add region creation support

Tue, 08 Jun 2021 17:28:34 +0000

cxl/region: Add region creation supportCXL 2.0 allows for dynamic provisioning of new memory regions (systemphysical address resources like "System RAM" and "Persistent Memory").Whereas DDR and PMEM resources are conveyed statically at boot, CXLallows for assembling and instantiating new regions from the availablecapacity of CXL memory expanders in the system.Sysfs with an "echo $region_name > $create_region_attribute" interfaceis chosen as the mechanism to initiate the provisioning process. Thiswas chosen over ioctl() and netlink() to keep the configurationinterface entirely in a pseudo-fs interface, and it was chosen overconfigfs since, aside from this one creation event, the interface isread-mostly. I.e. configfs supports cases where an object is designed tobe provisioned each boot, like an iSCSI storage target, and CXL regioncreation is mostly for PMEM regions which are created usually onceper-lifetime of a server instance. This is an improvement over nvdimmthat pre-created "seed" devices that tended to confuse users looking todetermine which devices are active and which are idle.Recall that the major change that CXL brings over previous persistentmemory architectures is the ability to dynamically define new regions.Compare that to drivers like 'nfit' where the region configuration isstatically defined by platform firmware.Regions are created as a child of a root decoder that encompasses anaddress space with constraints. When created through sysfs, the rootdecoder is explicit. When created from an LSA's region structure a rootdecoder will possibly need to be inferred by the driver.Upon region creation through sysfs, a vacant region is created with aunique name. Regions have a number of attributes that must be configuredbefore the region can be bound to the driver where HDM decoder programis completed.An example of creating a new region:- Allocate a new region name:region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)- Create a new region by name:whileregion=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_regiondo true; done- Region now exists in sysfs:stat -t /sys/bus/cxl/devices/decoder0.0/$region- Delete the region, and name:echo $region > /sys/bus/cxl/devices/decoder0.0/delete_regionSigned-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com[djbw: simplify locking, reword changelog]Signed-off-by: Dan Williams List of files: /linux-6.15/tools/testing/cxl/Kbuild