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    <title>Changes in Makefile</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>2672031b - riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#2672031b</link>
        <description>riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigThe BUILTIN_DTB_SOURCE was only configured for K210 before. SinceSOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f (&quot;riscv: Fixbuiltin DTB handling&quot;) from patch [1], the kernel cannot choose one of thedtbs from then on and always take the first one dtb to use. Then, anothercommit 0ddd7eaffa64 (&quot;riscv: Fix BUILTIN_DTB for sifive and microchip soc&quot;)from patch [2] supports BUILTIN_DTB_SOURCE for other SoCs. However, thisfeature will only work if the Kconfig we use links the dtb we expected inthe first place as mentioned in the thread [3]. Thus, a configBUILTIN_DTB_SOURCE is needed for all SoCs to choose one dtb to use.For some considerations, this patch also removes default y if XIP_KERNELfor BUILTIN_DTB, as this requires setting a proper dtb to use on theBUILTIN_DTB_SOURCE, else the kernel with XIP but does not setBUILTIN_DTB_SOURCE or unselect BUILTIN_DTB will not boot.Also, this patch removes the default dtb string for k210 from Kconfig tonommu_k210_defconfig and nommu_k210_sdcard_defconfig to avoid complexKconfig settings for other SoCs in the future.[1] https://lore.kernel.org/linux-riscv/20201208073355.40828-5-damien.lemoal@wdc.com/[2] https://lore.kernel.org/linux-riscv/20210604120639.1447869-1-alex@ghiti.fr/[3] https://lore.kernel.org/linux-riscv/CAK7LNATt_56mO2Le4v4EnPnAfd3gC8S_Sm5-GCsfa=qXy=8Lrg@mail.gmail.com/Signed-off-by: Yangyu Chen &lt;cyy@cyyself.name&gt;Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;Acked-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Wed, 28 Feb 2024 08:52:54 +0000</pubDate>
        <dc:creator>Yangyu Chen &lt;cyy@cyyself.name&gt;</dc:creator>
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        <title>19ba9cf7 - RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#19ba9cf7</link>
        <description>RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConvert all non user visible use of SOC_FOO symbols to their ARCH_FOOvariants. The canaan DTs are an outlier in that they&apos;re gated at thedirectory and the file level. Drop the directory level gating while weare swapping the symbol names over.Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Sun, 20 Nov 2022 21:34:44 +0000</pubDate>
        <dc:creator>Conor Dooley &lt;conor.dooley@microchip.com&gt;</dc:creator>
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        <title>0ddd7eaf - riscv: Fix BUILTIN_DTB for sifive and microchip soc</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#0ddd7eaf</link>
        <description>riscv: Fix BUILTIN_DTB for sifive and microchip socFix BUILTIN_DTB config which resulted in a dtb that was actually notbuilt into the Linux image: in the same manner as Canaan soc does,create an object file from the dtb file that will get linked into theLinux image.Signed-off-by: Alexandre Ghiti &lt;alex@ghiti.fr&gt;Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Fri, 04 Jun 2021 12:06:39 +0000</pubDate>
        <dc:creator>Alexandre Ghiti &lt;alex@ghiti.fr&gt;</dc:creator>
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        <title>d573b555 - riscv: dts: add initial board data for the SiFive HiFive Unmatched</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#d573b555</link>
        <description>riscv: dts: add initial board data for the SiFive HiFive UnmatchedAdd initial board data for the SiFive HiFive Unmatched A00.This patch is dependent on Zong&apos;s Patchset[0].[0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#uSigned-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Tue, 08 Dec 2020 04:55:41 +0000</pubDate>
        <dc:creator>Yash Shah &lt;yash.shah@sifive.com&gt;</dc:creator>
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        <title>0cbb8a32 - arch: riscv: add config option for building SiFive&apos;s SoC resource</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#0cbb8a32</link>
        <description>arch: riscv: add config option for building SiFive&apos;s SoC resourceCreate a config option for building SiFive SoC specific resourcese.g. SiFive device tree, platform drivers...Signed-off-by: Loys Ollivier &lt;lollivier@baylibre.com&gt;Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Mon, 17 Jun 2019 19:29:48 +0000</pubDate>
        <dc:creator>Loys Ollivier &lt;lollivier@baylibre.com&gt;</dc:creator>
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        <title>c35f1b87 - riscv: dts: add initial board data for the SiFive HiFive Unleashed</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile#c35f1b87</link>
        <description>riscv: dts: add initial board data for the SiFive HiFive UnleashedAdd initial board data for the SiFive HiFive Unleashed A00.Currently the data populated in this DT file describes the boardDRAM configuration and the external clock sources that supply thePRCI.Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;Tested-by: Loys Ollivier &lt;lollivier@baylibre.com&gt;Tested-by: Kevin Hilman &lt;khilman@baylibre.com&gt;Cc: Rob Herring &lt;robh+dt@kernel.org&gt;Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;Cc: Antony Pavlov &lt;antonynpavlov@gmail.com&gt;Cc: devicetree@vger.kernel.orgCc: linux-riscv@lists.infradead.orgCc: linux-kernel@vger.kernel.org

            List of files:
            /linux-6.15/scripts/dtc/include-prefixes/riscv/sifive/Makefile</description>
        <pubDate>Mon, 20 May 2019 16:19:41 +0000</pubDate>
        <dc:creator>Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</dc:creator>
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