Changes in Makefile

3f41368f - riscv: dts: microchip: add an initial devicetree for the BeagleV Fire

Wed, 27 Mar 2024 12:24:40 +0000

riscv: dts: microchip: add an initial devicetree for the BeagleV FireAdd an initial devicetree for the BeagleV Fire. This devicetree differsfrom that in the BeagleBoard BSP as it has a different memoryconfiguration, however it will boot on the same FPGA images. PCI isdisabled for now, as the Linux PCI driver (and the binding) assumewhich root port instance is in use. This will need to be fixed beforePCI can be enabled.Link: https://www.beagleboard.org/boards/beaglev-fireCo-developed-by: Jamie Gibbons Signed-off-by: Jamie Gibbons Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

2672031b - riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig

Wed, 28 Feb 2024 08:52:54 +0000

riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigThe BUILTIN_DTB_SOURCE was only configured for K210 before. SinceSOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f ("riscv: Fixbuiltin DTB handling") from patch [1], the kernel cannot choose one of thedtbs from then on and always take the first one dtb to use. Then, anothercommit 0ddd7eaffa64 ("riscv: Fix BUILTIN_DTB for sifive and microchip soc")from patch [2] supports BUILTIN_DTB_SOURCE for other SoCs. However, thisfeature will only work if the Kconfig we use links the dtb we expected inthe first place as mentioned in the thread [3]. Thus, a configBUILTIN_DTB_SOURCE is needed for all SoCs to choose one dtb to use.For some considerations, this patch also removes default y if XIP_KERNELfor BUILTIN_DTB, as this requires setting a proper dtb to use on theBUILTIN_DTB_SOURCE, else the kernel with XIP but does not setBUILTIN_DTB_SOURCE or unselect BUILTIN_DTB will not boot.Also, this patch removes the default dtb string for k210 from Kconfig tonommu_k210_defconfig and nommu_k210_sdcard_defconfig to avoid complexKconfig settings for other SoCs in the future.[1] https://lore.kernel.org/linux-riscv/20201208073355.40828-5-damien.lemoal@wdc.com/[2] https://lore.kernel.org/linux-riscv/20210604120639.1447869-1-alex@ghiti.fr/[3] https://lore.kernel.org/linux-riscv/CAK7LNATt_56mO2Le4v4EnPnAfd3gC8S_Sm5-GCsfa=qXy=8Lrg@mail.gmail.com/Signed-off-by: Yangyu Chen Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

497e6b37 - riscv: dts: microchip: add the Aldec TySoM's devicetree

Wed, 11 Jan 2023 12:41:07 +0000

riscv: dts: microchip: add the Aldec TySoM's devicetreeThe TySOM-M-MPFS250 is a compact SoC prototyping board featuringa Microchip PolarFire SoC MPFS250T-FCG1152. Features include:- 16 Gib FPGA DDR4- 16 Gib MSS DDR4 with ECC- eMMC- SPI flash memory- 2x Ethernet 10/100/1000- USB 2.0- PCIe x4 Gen2- HDMI OUT- 2x FMC connector (HPC and LPC)Specifically flag this board as rev2, in case later boards have anFPGA design revision with more features available in the future.Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250[Fixed a mistake where I read 16 Gib as 16 GiB!]Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

19ba9cf7 - RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO

Sun, 20 Nov 2022 21:34:44 +0000

RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConvert all non user visible use of SOC_FOO symbols to their ARCH_FOOvariants. The canaan DTs are an outlier in that they're gated at thedirectory and the file level. Drop the directory level gating while weare swapping the symbol names over.Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

d4916664 - riscv: dts: microchip: add a devicetree for aries' m100pfsevp

Tue, 27 Sep 2022 11:19:22 +0000

riscv: dts: microchip: add a devicetree for aries' m100pfsevpAdd device trees for both configs used by the Aries EmbeddedM100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,featuring:- 2GB DDR4 SDRAM dedicated to the HMS- 512MB DDR4 SDRAM dedicated to the FPGA- 32 MB SPI NOR Flash- 4 GByte eMMCand a carrier board with:- 2x Gigabit Ethernet- USB- 2x UART- 2x CAN- TFT connector- HSMC extension connector- 3x PMOD extension connectors- microSD-card slotLink: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdesLink: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmodLink: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdfCo-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

978a17d1 - riscv: dts: microchip: add sevkit device tree

Tue, 27 Sep 2022 11:19:21 +0000

riscv: dts: microchip: add sevkit device treeAdd a basic dts for the Microchip Smart Embedded Vision dev kit.The SEV kit is an upcoming first party board, featuring an MPFS250T and:- Dual Sony Camera Sensors (IMX334)- IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi- Bluetooth 5 Low Energy- 4 GB DDR4 x64- 2 GB LPDDR4 x32- 1 GB SPI Flash- 8 GB eMMC flash & SD card slot (multiplexed)- HDMI2.0 Video Input/Output- MIPI DSI Output- MIPI CSI-2 InputLink: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06Signed-off-by: Vattipalli Praveen Signed-off-by: Conor Dooley List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

bc47b221 - riscv: dts: microchip: add the sundance polarberry

Mon, 09 May 2022 14:26:09 +0000

riscv: dts: microchip: add the sundance polarberryAdd a minimal device tree for the PolarFire SoC based SundancePolarBerry.Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

da305fa8 - riscv: dts: microchip: remove soc vendor from filenames

Mon, 09 May 2022 14:26:04 +0000

riscv: dts: microchip: remove soc vendor from filenamesHaving the SoC vendor both as the directory and in the filename addslittle. Remove microchip from the filenames so that the files willresemble the other directories in riscv (and arm64). The new namesfollow a soc-board.dts & soc{,-fabric}.dtsi pattern.Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220509142610.128590-4-conor.dooley@microchip.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

0ddd7eaf - riscv: Fix BUILTIN_DTB for sifive and microchip soc

Fri, 04 Jun 2021 12:06:39 +0000

riscv: Fix BUILTIN_DTB for sifive and microchip socFix BUILTIN_DTB config which resulted in a dtb that was actually notbuilt into the Linux image: in the same manner as Canaan soc does,create an object file from the dtb file that will get linked into theLinux image.Signed-off-by: Alexandre Ghiti Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile

0fa6107e - RISC-V: Initial DTS for Microchip ICICLE board

Wed, 03 Mar 2021 20:02:51 +0000

RISC-V: Initial DTS for Microchip ICICLE boardAdd initial DTS for Microchip ICICLE board having onlyessential devices (clocks, sdhci, ethernet, serial, etc).The device tree is based on the U-Boot patch.https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/Signed-off-by: Atish Patra Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/scripts/dtc/include-prefixes/riscv/microchip/Makefile