Changes in Makefile

df7f9acd - platform/x86: intel: Add 'intel' prefix to the modules automatically

Wed, 16 Oct 2024 10:59:51 +0000

platform/x86: intel: Add 'intel' prefix to the modules automaticallyRework Makefile to add 'intel' prefix to the modules automatically.This removes a lot of boilerplate code in it and also makes robustagainst mistypos in the prefix.Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20241016105950.785820-2-andriy.shevchenko@linux.intel.comReviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

811f67c5 - platform/x86/intel/tpmi: Add new auxiliary driver for performance limits

Mon, 27 May 2024 13:29:36 +0000

platform/x86/intel/tpmi: Add new auxiliary driver for performance limitsAdd new auxiliary driver that exposes the SoC performance limit reasonsvia debugfs interface.Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo Järvinen Signed-off-by: Tero Kristo Link: https://lore.kernel.org/r/20240527133400.483634-5-tero.kristo@linux.intel.comSigned-off-by: Ilpo Järvinen List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

17ca2780 - platform/x86/intel: TPMI domain id and CPU mapping

Tue, 28 May 2024 07:34:57 +0000

platform/x86/intel: TPMI domain id and CPU mappingEach TPMI power domain includes a group of CPUs. Several powermanagement settings in this case applicable to a group of CPUs.There can be several power domains in a CPU package. So, provideinterfaces for:- Get power domain id for a Linux CPU- Get mask of Linux CPUs in a power domainHardware Punit uses different CPU numbering, which is not based onAPIC (Advanced Programmable Interrupt Controller) CPU numbering.The Linux CPU numbering is based on APIC CPU numbering. Some PM featureslike Intel Speed Select, the CPU core mask provided by the hardware isbased on the Punit CPU numbering. To use the core mask, this maskneeds to be converted to a Linux CPUs mask. So, provide interfaces for:- Convert to a Linux CPU number from a Punit CPU number- Convert to a Punit CPU number from a Linux CPU numberOn each CPU online, MSR 0x54 is used to read the mapping and stores ina per cpu array. Create a hash for faster searching of a Linux CPU numberfrom a Punit CPU number.Signed-off-by: Srinivas Pandruvada [tero.kristo: minor updates]Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo Järvinen Signed-off-by: Tero Kristo Link: https://lore.kernel.org/r/20240528073457.497816-1-tero.kristo@linux.intel.comSigned-off-by: Ilpo Järvinen List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

94227b9c - platform/x86: Add intel_bytcrc_pwrsrc driver

Fri, 03 Mar 2023 22:19:28 +0000

platform/x86: Add intel_bytcrc_pwrsrc driverAdd a new driver for the power-, wake- and reset-source functionalityof the Bay Trail (BYT) version of the Crystal Cove PMIC.The main functionality here is detecting which power-sources (USB /DC in / battery) are active. This is normally exposed to userspace asa power_supply class charger device with an online sysfs attribute.But if a charger is online or not is already exposed on BYT-CRC devicesthrough either an ACPI AC power_supply device, or through a native driverfor the battery charger chip (e.g. a BQ24292i).So instead of adding duplicate info under the power_supply class thisdriver exports the info through debugfs and likewise adds debugfs filesfor the reset- and wake-source info / registers.Despite this driver only exporting debugfs bits it is still useful tohave this driver because it clears the wake- and reset-source registersafter reading them. Not clearing these can have undesirable side-effects.Specifically if the WAKESRC register contains 0x01 (wake by powerbutton)on reboot then the firmware on some tablets turns the reboot intoa poweroff. I guess this may be necessary to make long power-presses turninto a poweroff somehow?Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20230303221928.285477-1-hdegoede@redhat.com List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

47731fd2 - platform/x86/intel: Intel TPMI enumeration driver

Thu, 02 Feb 2023 01:07:35 +0000

platform/x86/intel: Intel TPMI enumeration driverThe TPMI (Topology Aware Register and PM Capsule Interface) provides aflexible, extendable and PCIe enumerable MMIO interface for PM features.For example Intel RAPL (Running Average Power Limit) provides a MMIOinterface using TPMI. This has advantage over traditional MSR(Model Specific Register) interface, where a thread needs to be scheduledon the target CPU to read or write. Also the RAPL features vary betweenCPU models, and hence lot of model specific code. Here TPMI provides anarchitectural interface by providing hierarchical tables and fields,which will not need any model specific implementation.The TPMI interface uses a PCI VSEC structure to expose the location ofMMIO region.This VSEC structure is present in the PCI configuration space of theIntel Out-of-Band (OOB) device, which is handled by the Intel VSECdriver. The Intel VSEC driver parses VSEC structures present in the PCIconfiguration space of the given device and creates an auxiliary deviceobject for each of them. In particular, it creates an auxiliary deviceobject representing TPMI that can be bound by an auxiliary driver.Introduce a TPMI driver that will bind to the TPMI auxiliary deviceobject created by the Intel VSEC driver.The TPMI specification defines a PFS (PM Feature Structure) table.This table is present in the TPMI MMIO region. The starting addressof PFS is derived from the tBIR (Bar Indicator Register) and "Address"field from the VSEC header.Each TPMI PM feature has one entry in the PFS with a unique TPMIID and its access details. The TPMI driver creates device nodesfor the supported PM features.The names of the devices created by the TPMI driver start with the"intel_vsec.tpmi-" prefix which is followed by a specific name of thegiven PM feature (for example, "intel_vsec.tpmi-rapl.0").The device nodes are create by using interface "intel_vsec_add_aux()"provided by the Intel VSEC driver.Signed-off-by: Srinivas Pandruvada Reviewed-by: Pierre-Louis Bossart Acked-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/20230202010738.2186174-5-srinivas.pandruvada@linux.intel.comReviewed-by: Hans de Goede Signed-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

42d0d423 - platform/x86: p2sb: Move out of X86_PLATFORM_DEVICES dependency

Mon, 18 Jul 2022 14:53:28 +0000

platform/x86: p2sb: Move out of X86_PLATFORM_DEVICES dependencyThe P2SB library is used for various drivers, including serverplatforms. That's why the dependency on X86_PLATFORM_DEVICESseems superfluous.Reported-by: kernel test robot Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20220718145328.14374-1-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

9745fb07 - platform/x86/intel: Add Primary to Sideband (P2SB) bridge support

Mon, 06 Jun 2022 16:41:27 +0000

platform/x86/intel: Add Primary to Sideband (P2SB) bridge supportSoC features such as GPIO are accessed via a reserved MMIO area,we don't know its address but can obtain it from the BAR ofthe P2SB device, that device is normally hidden so we have totemporarily unhide it, read address and hide it back.There are already a few users and at least one more is coming whichrequire an access to Primary to Sideband (P2SB) bridge in orderto get IO or MMIO BAR hidden by BIOS.Create a library to access P2SB for x86 devices in a unified way.Background information======================Note, the term "bridge" is used in the documentation and it has nothingto do with a PCI (host) bridge as per the PCI specifications.The P2SB is an interesting device by its nature and hardware design.First of all, it has several devices in the hardware behind it. Thesedevices may or may not be represented as ACPI devices by a firmware.It also has a hardwired (to 0s) the least significant bits of thebase address register which is represented by the only 64-bit BAR0.It means that OS mustn't reallocate the BAR.On top of that in some cases P2SB is represented by function 0 on PCIslot (in terms of B:D.F) and according to the PCI specification anyother function can't be seen until function 0 is present and visible.In the PCI configuration space of P2SB device the full 32-bit registeris allocated for the only purpose of hiding the entire P2SB device. Asper [3]: 3.1.39 P2SB Control (P2SBC)—Offset E0h Hide Device (HIDE): When this bit is set, the P2SB will return 1s on any PCI Configuration Read on IOSF-P. All other transactions including PCI Configuration Writes on IOSF-P are unaffected by this. This does not affect reads performed on the IOSF-SB interface.This doesn't prevent MMIO accesses, although preventing the OS fromassigning these addresses. The firmware on the affected platforms marksthe region as unusable (by cutting it off from the PCI host bridgeresources) as depicted in the Apollo Lake example below: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x0070-0x0077] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] pci_bus 0000:00: root bus resource [mem 0x7b800001-0x7bffffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] pci_bus 0000:00: root bus resource [bus 00-ff]The P2SB 16MB BAR is located at 0xd0000000-0xd0ffffff memory window.The generic solution====================The generic solution for all cases when we need to access to the informationbehind P2SB device is a library code where users ask for necessary resourcesby demand and hence those users take care of not being run on the systemswhere this access is not required.The library provides the p2sb_bar() API to retrieve the MMIO of the BAR0 ofthe device from P2SB device slot.P2SB unconditional unhiding awareness=====================================Technically it's possible to unhide the P2SB device and devices onthe same PCI slot and access them at any time as needed. But there areseveral potential issues with that: - the systems were never tested against such configuration and hence nobody knows what kind of bugs it may bring, especially when we talk about SPI NOR case which contains Intel FirmWare Image (IFWI) code (including BIOS) and already known to be problematic in the past for end users - the PCI by its nature is a hotpluggable bus and in case somebody attaches a driver to the functions of a P2SB slot device(s) the end user experience and system behaviour can be unpredictable - the kernel code would need some ugly hacks (or code looking as an ugly hack) under arch/x86/pci in order to enable these devices on only selected platforms (which may include CPU ID table followed by a potentially growing number of DMI stringsThe future improvements=======================The future improvements with this code may go in order to gain some kindof cache, if it's possible at all, to prevent unhiding and hiding manytimes to take static information that may be saved once per boot.Links=====[1]: https://lab.whitequark.org/notes/2017-11-08/accessing-intel-ich-pch-gpios/[2]: https://cdrdv2.intel.com/v1/dl/getContent/332690?wapkw=332690[3]: https://cdrdv2.intel.com/v1/dl/getContent/332691?wapkw=332691[4]: https://medium.com/@jacksonchen_43335/bios-gpio-p2sb-70e9b829b403Signed-off-by: Jonathan Yong Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko Tested-by: Henning Schild Acked-by: Hans de Goede Acked-by: Linus Walleij Signed-off-by: Lee Jones List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

67896ef1 - platform/x86/intel/ifs: Add stub driver for In-Field Scan

Fri, 06 May 2022 22:54:02 +0000

platform/x86/intel/ifs: Add stub driver for In-Field ScanCloud Service Providers that operate fleets of servers have reported[1] occasions where they can detect that a CPU has gone bad due toeffects like electromigration, or isolated manufacturing defects.However, that detection method is A/B testing seemingly randomapplication failures looking for a pattern. In-Field Scan (IFS) isa driver for a platform capability to load a crafted 'scan image'to run targeted low level diagnostics outside of the CPU's architecturalerror detection capabilities.Stub version of driver just does initial part of check for the IFSfeature. MSR_IA32_CORE_CAPS must enumerate the presence of theMSR_INTEGRITY_CAPS MSR.[1]: https://www.youtube.com/watch?v=QMF3rqhjYuMReviewed-by: Dan Williams Signed-off-by: Tony Luck Acked-by: Hans de Goede Reviewed-by: Greg Kroah-Hartman Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20220506225410.1652287-5-tony.luck@intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

ce2645c4 - platform/x86/intel/uncore-freq: Move to uncore-frequency folder

Fri, 04 Feb 2022 00:03:03 +0000

platform/x86/intel/uncore-freq: Move to uncore-frequency folderMove the current driver from platform/x86/intel/uncore-frequency.cto platform/x86/intel/uncore-frequency/uncore-frequency.c.No functional changes are expected.Signed-off-by: Srinivas Pandruvada Acked-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/20220204000306.2517447-2-srinivas.pandruvada@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

2546c600 - platform/x86: Add Intel Software Defined Silicon driver

Sat, 12 Feb 2022 01:32:50 +0000

platform/x86: Add Intel Software Defined Silicon driverIntel Software Defined Silicon (SDSi) is a post manufacturing mechanism foractivating additional silicon features. Features are enabled through alicense activation process. The SDSi driver provides a per socket, sysfsattribute interface for applications to perform 3 main provisioningfunctions:1. Provision an Authentication Key Certificate (AKC), a key written to internal NVRAM that is used to authenticate a capability specific activation payload.2. Provision a Capability Activation Payload (CAP), a token authenticated using the AKC and applied to the CPU configuration to activate a new feature.3. Read the SDSi State Certificate, containing the CPU configuration state.The operations perform function specific mailbox commands that forward therequests to SDSi hardware to perform authentication of the payloads andenable the silicon configuration (to be made available after powercycling).The SDSi device itself is enumerated as an auxiliary device from theintel_vsec driver and as such has a build dependency on CONFIG_INTEL_VSEC.Link: https://github.com/intel/intel-sdsiSigned-off-by: David E. Box Reviewed-by: Mark Gross Link: https://lore.kernel.org/r/20220212013252.1293396-2-david.e.box@linux.intel.comReviewed-by: Hans de Goede Signed-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

ae707d0e - platform/x86: intel_cht_int33fe: Move to intel directory

Sun, 06 Feb 2022 22:02:20 +0000

platform/x86: intel_cht_int33fe: Move to intel directoryNow that there is only 1 c-file left of the intel_cht_int33fe code,move it to the intel directory instead of it having its own int33fesub-directory.Note this also renames the module from intel_cht_int33fe_typec tointel_chtwc_int33fe, to better match the names of other PMIC relatedmodules like the intel_chtdc_ti_pwrbtn module.Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20220206220220.88491-4-hdegoede@redhat.com List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

761db353 - platform/x86: Add intel_crystal_cove_charger driver

Sat, 25 Dec 2021 11:55:09 +0000

platform/x86: Add intel_crystal_cove_charger driverDriver for the external-charger IRQ pass-through function of theIntel Bay Trail Crystal Cove PMIC.Note this is NOT a power_supply class driver, it just deals with IRQpass-through, this requires this separate driver because the PMIC'slevel 2 interrupt for this must be explicitly acked.This new driver gets enabled by the existing X86_ANDROID_TABLETS Kconfigoption because the x86-android-tablets module is the only consumer of theexported external-charger IRQ.Reviewed-by: Andy Shevchenko Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20211225115509.94891-5-hdegoede@redhat.com List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

a3c8f906 - platform/x86/intel: Move intel_pmt from MFD to Auxiliary Bus

Wed, 08 Dec 2021 01:50:12 +0000

platform/x86/intel: Move intel_pmt from MFD to Auxiliary BusIntel Platform Monitoring Technology (PMT) support is indicated by presenceof an Intel defined PCIe Designated Vendor Specific Extended Capabilities(DVSEC) structure with a PMT specific ID. The current MFD implementationcreates child devices for each PMT feature, currently telemetry, watcher,and crashlog. However DVSEC structures may also be used by Intel toindicate support for other features. The Out Of Band Management ServicesModule (OOBMSM) uses DVSEC to enumerate several features, including PMT.In order to support them it is necessary to modify the intel_pmt driver tohandle the creation of the child devices more generically. To that end,modify the driver to create child devices for any VSEC/DVSEC features onsupported devices (indicated by PCI ID). Additionally, move theimplementation from MFD to the Auxiliary bus. VSEC/DVSEC features arereally multifunctional PCI devices, not platform devices as MFD wasdesigned for. Auxiliary bus gives more flexibility by allowing thedefinition of custom structures that can be shared between associatedauxiliary devices and the parent device. Also, rename the driver fromintel_pmt to intel_vsec to better reflect the purpose.This series also removes the current runtime pm support which was notcomplete to begin with. None of the current devices require runtime pm.However the support will be replaced when a device is added that requiresit.Reviewed-by: Mark Gross Acked-by: Hans de Goede Signed-off-by: David E. Box Link: https://lore.kernel.org/r/20211208015015.891275-4-david.e.box@linux.intel.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

7b6bf51d - platform/x86: Add Intel ishtp eclite driver

Mon, 13 Sep 2021 05:10:56 +0000

platform/x86: Add Intel ishtp eclite driverThis driver is for accessing the PSE (Programmable Service Engine) - anEmbedded Controller like IP - using ISHTP (Integratd Sensor Hub TransportProtocol) to get battery, thermal and UCSI (USB Type-C Connector SystemSoftware Interface) related data from the platform.Signed-off-by: K Naduvalath, Sumesh Reviewed-by: Mark Gross Link: https://lore.kernel.org/r/20210913051056.28736-1-sumesh.k.naduvalath@intel.comReviewed-by: Hans de Goede Signed-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

bd5b4fb4 - platform/x86: intel-wmi-sbl-fw-update: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:57 +0000

platform/x86: intel-wmi-sbl-fw-update: Move to intel sub-directoryMove Intel WMI Slim Bootloader FW update driver to intel sub-directoryto improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-20-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

3afeacfd - platform/x86: intel-vbtn: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:56 +0000

platform/x86: intel-vbtn: Move to intel sub-directoryMove Intel vButton driver to intel sub-directory to improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-19-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

cdbb8f5e - platform/x86: intel_oaktrail: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:55 +0000

platform/x86: intel_oaktrail: Move to intel sub-directoryMove Intel Oaktrail driver to intel sub-directory to improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-18-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

daef4c5a - platform/x86: intel_int0002_vgpio: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:54 +0000

platform/x86: intel_int0002_vgpio: Move to intel sub-directoryMove Intel vGPIO (INT0002) driver to intel sub-directoryto improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-17-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

c3d3586d - platform/x86: intel-hid: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:53 +0000

platform/x86: intel-hid: Move to intel sub-directoryMove Intel HID driver to intel sub-directory to improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-16-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile

76693f57 - platform/x86: intel_atomisp2: Move to intel sub-directory

Fri, 20 Aug 2021 11:04:52 +0000

platform/x86: intel_atomisp2: Move to intel sub-directoryMove Intel AtomISP v2 drivers to intel sub-directoryto improve readability.Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210820110458.73018-15-andriy.shevchenko@linux.intel.comSigned-off-by: Hans de Goede List of files: /linux-6.15/drivers/platform/x86/intel/Makefile