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    <title>Changes in Makefile</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>e52a6321 - phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/phy/lantiq/Makefile#e52a6321</link>
        <description>phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHYThe Lantiq VRX200 SoCs embed a PCIe PHY in the &quot;sram&quot; bus. Unlike mostother IP blocks on this SoC the register values are only 16-bit wide.Like other IP blocks on this SoC the register values are in big endian.The PHY embeds a PLL which can be configured in various modes. Only the36MHz mode is supported for now, the other modes can be implemented whenthere&apos;s a board which actually needs them. OpenWrt uses the out-of-treevendor driver and all supported boards there only need the 36MHz mode.There are two input clocks:- the &quot;pdi&quot; clock enables the register access- the &quot;phy&quot; clock is the clock input and enables the internal PLLThere are two reset lines:- &quot;phy&quot; resets the PHY itself- the &quot;pcie&quot; reset line is shared between the PHY and the PCIe  controllerWhile the VRX200 SoC has only one PCIe controller and PHY the ARX300uses two identical PCIe controllers and PHYs which are compatible withthe PCIe controller and PHY on VRX200.Add a driver for this PHY so PCIe support can be enabled on these SoCs.Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;

            List of files:
            /linux-6.15/drivers/phy/lantiq/Makefile</description>
        <pubDate>Sat, 27 Jul 2019 12:04:13 +0000</pubDate>
        <dc:creator>Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;</dc:creator>
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        <title>ec8f24b7 - treewide: Add SPDX license identifier - Makefile/Kconfig</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/phy/lantiq/Makefile#ec8f24b7</link>
        <description>treewide: Add SPDX license identifier - Makefile/KconfigAdd SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any formThese files fall under the project license, GPL v2 only. The resulting SPDXlicense identifier is:  GPL-2.0-onlySigned-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

            List of files:
            /linux-6.15/drivers/phy/lantiq/Makefile</description>
        <pubDate>Sun, 19 May 2019 12:07:45 +0000</pubDate>
        <dc:creator>Thomas Gleixner &lt;tglx@linutronix.de&gt;</dc:creator>
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        <title>dea54fba - phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/phy/lantiq/Makefile#dea54fba</link>
        <description>phy: Add an USB PHY driver for the Lantiq SoCs using the RCU moduleThis driver starts the DWC2 core(s) built into the XWAY SoCs and providesthe PHY interfaces for each core. The phy instances can be passed to thedwc2 driver, which already supports the generic phy interface.Signed-off-by: Hauke Mehrtens &lt;hauke@hauke-m.de&gt;Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;Acked-by: Rob Herring &lt;robh@kernel.org&gt;Cc: martin.blumenstingl@googlemail.comCc: john@phrozen.orgCc: andy.shevchenko@gmail.comCc: p.zabel@pengutronix.deCc: mark.rutland@arm.comCc: linux-mips@linux-mips.orgCc: linux-mtd@lists.infradead.orgCc: linux-watchdog@vger.kernel.orgCc: devicetree@vger.kernel.orgCc: linux-spi@vger.kernel.orgPatchwork: https://patchwork.linux-mips.org/patch/17127/Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;

            List of files:
            /linux-6.15/drivers/phy/lantiq/Makefile</description>
        <pubDate>Sat, 19 Aug 2017 22:18:21 +0000</pubDate>
        <dc:creator>Hauke Mehrtens &lt;hauke@hauke-m.de&gt;</dc:creator>
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