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    <title>Changes in Makefile</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>f6bb3e9d - net: pcs: xpcs: Add Synopsys DW xPCS platform device driver</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#f6bb3e9d</link>
        <description>net: pcs: xpcs: Add Synopsys DW xPCS platform device driverSynopsys DesignWare XPCS IP-core can be synthesized with the device CSRsbeing accessible over the MCI or APB3 interface instead of the MDIO bus(see the CSR_INTERFACE HDL parameter). Thus all the PCS registers can bejust memory mapped and be a subject of the standard MMIO operations ofcourse taking into account the peculiarities of the Clause C45 CSRsmapping. From that perspective the DW XPCS devices would look as justnormal platform devices for the kernel.On the other hand in order to have the DW XPCS devices handled by thepcs-xpcs.c driver they need to be registered in the framework of theMDIO-subsystem. So the suggested change is about providing a DW XPCSplatform device driver registering a virtual MDIO-bus with a singleMDIO-device representing the DW XPCS device.DW XPCS platform device is supposed to be described by the respectivecompatible string &quot;snps,dw-xpcs&quot; (or with the PMA-specific compatiblestring), CSRs memory space and optional peripheral bus and reference clocksources. Depending on the INDIRECT_ACCESS IP-core synthesize parameter thememory-mapped reg-space can be represented as either directly orindirectly mapped Clause 45 space. In the former case the particularaddress is determined based on the MMD device and the registers offset (5+ 16 bits all together) within the device reg-space. In the later casethere is only 8 lower address bits are utilized for the registers mapping(255 CSRs). The upper bits are supposed to be written into the respectiveviewport CSR in order to select the respective MMD sub-page.Note, only the peripheral bus clock source is requested in the platformdevice probe procedure. The core and pad clocks handling has beenimplemented in the framework of the xpcs_create() method intentionallysince the clocks-related setups are supposed to be performed later, duringthe DW XPCS main configuration procedures. (For instance they will berequired for the DW Gen5 10G PMA configuration.)Signed-off-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Mon, 01 Jul 2024 18:28:38 +0000</pubDate>
        <dc:creator>Serge Semin &lt;fancer.lancer@gmail.com&gt;</dc:creator>
    </item>
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        <title>f629acc6 - net: pcs: xpcs: support to switch mode for Wangxun NICs</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#f629acc6</link>
        <description>net: pcs: xpcs: support to switch mode for Wangxun NICsAccording to chapter 6 of DesignWare Cores Ethernet PCS (version 3.20a)and custom design manual, add a configuration flow for switching interfacemode.If the interface changes, the following setting is required:1. wait VR_XS_PCS_DIG_STS bit(4, 2) [PSEQ_STATE] = 100b (Power-Good)2. write SR_XS_PCS_CTRL2 to select various PCS type3. write SR_PMA_CTRL1 and/or SR_XS_PCS_CTRL1 for link speed4. program PMA registers5. write VR_XS_PCS_DIG_CTRL1 bit(15) [VR_RST] = 1b (Vendor-Specific   Soft Reset)6. wait for VR_XS_PCS_DIG_CTRL1 bit(15) [VR_RST] to get clearedOnly 10GBASE-R/SGMII/1000BASE-X modes are planned for the current Wangxundevices. And there is a quirk for Wangxun devices to switch mode althoughthe interface in phylink state has not changed, since PCS will change todefault 10GBASE-R when the ethernet driver(txgbe) do LAN reset.Signed-off-by: Jiawen Wu &lt;jiawenwu@trustnetic.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Wed, 23 Aug 2023 06:19:29 +0000</pubDate>
        <dc:creator>Jiawen Wu &lt;jiawenwu@trustnetic.com&gt;</dc:creator>
    </item>
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        <title>196eec40 - net: pcs: Drop the TSE PCS driver</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#196eec40</link>
        <description>net: pcs: Drop the TSE PCS driverNow that we can easily create a mdio-device that represents amemory-mapped device that exposes an MDIO-like register layout, we don&apos;tneed the Altera TSE PCS anymore, since we can use the Lynx PCS instead.Reviewed-by: Simon Horman &lt;simon.horman@corigine.com&gt;Signed-off-by: Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Thu, 01 Jun 2023 14:14:53 +0000</pubDate>
        <dc:creator>Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;</dc:creator>
    </item>
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        <title>4765a972 - net: pcs: add driver for MediaTek SGMII PCS</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#4765a972</link>
        <description>net: pcs: add driver for MediaTek SGMII PCSThe SGMII core found in several MediaTek SoCs is identical to what canalso be found in MediaTek&apos;s MT7531 Ethernet switch IC.As this has not always been clear, both drivers developed differentimplementations to deal with the PCS.Recently Alexander Couzens pointed out this fact which lead to thedevelopment of this shared driver.Add a dedicated driver, mostly by copying the code now found in theEthernet driver. The now redundant code will be removed by a follow-upcommit.Suggested-by: Alexander Couzens &lt;lynxis@fe80.eu&gt;Suggested-by: Russell King (Oracle) &lt;rmk+kernel@armlinux.org.uk&gt;Signed-off-by: Daniel Golle &lt;daniel@makrotopia.org&gt;Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;Reviewed-by: Russell King (Oracle) &lt;rmk+kernel@armlinux.org.uk&gt;Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Sun, 19 Mar 2023 12:57:50 +0000</pubDate>
        <dc:creator>Daniel Golle &lt;daniel@makrotopia.org&gt;</dc:creator>
    </item>
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        <title>4a502cf4 - net: pcs: add new PCS driver for altera TSE PCS</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#4a502cf4</link>
        <description>net: pcs: add new PCS driver for altera TSE PCSThe Altera Triple Speed Ethernet has a SGMII/1000BaseC PCS that can beintegrated in several ways. It can either be part of the TSE MAC&apos;saddress space, accessed through 32 bits accesses on the mapped mdiodevice 0, or through a dedicated 16 bits register set.This driver allows using the TSE PCS outside of altera TSE&apos;s driver,since it can be used standalone by other MACs.Signed-off-by: Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Fri, 02 Sep 2022 08:32:03 +0000</pubDate>
        <dc:creator>Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;</dc:creator>
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        <title>7dc54d3b - net: pcs: add Renesas MII converter driver</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#7dc54d3b</link>
        <description>net: pcs: add Renesas MII converter driverAdd a PCS driver for the MII converter that is present on the RenesasRZ/N1 SoC. This MII converter is reponsible for converting MII toRMII/RGMII or act as a MII pass-trough. Exposing it as a PCS allows toreuse it in both the switch driver and the stmmac driver. Currently,this driver only allows the PCS to be used by the dual Cortex-A7subsystem since the register locking system is not used.Signed-off-by: Cl&#233;ment L&#233;ger &lt;clement.leger@bootlin.com&gt;Reviewed-by: Vladimir Oltean &lt;olteanv@gmail.com&gt;Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Fri, 24 Jun 2022 14:39:50 +0000</pubDate>
        <dc:creator>Cl&#233;ment L&#233;ger &lt;clement.leger@bootlin.com&gt;</dc:creator>
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<item>
        <title>dd0721ea - net: pcs: xpcs: add support for NXP SJA1105</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#dd0721ea</link>
        <description>net: pcs: xpcs: add support for NXP SJA1105The NXP SJA1105 DSA switch integrates a Synopsys SGMII XPCS on port 4.The generic code works fine, except there is an integration issue whichneeds to be dealt with: in this switch, the XPCS is integrated with aPMA that has the TX lane polarity inverted by default (PLUS is MINUS,MINUS is PLUS).To obtain normal non-inverted behavior, the TX lane polarity must beinverted in the PCS, via the DIGITAL_CONTROL_2 register.We introduce a pma_config() method in xpcs_compat which is called by thephylink_pcs_config() implementation.Also, the NXP SJA1105 returns all zeroes in the PHY ID registers 2 and 3.We need to hack up an ad-hoc PHY ID (OUI is zero, device ID is 1) inorder for the XPCS driver to recognize it. This PHY ID is added to thepublic include/linux/pcs/pcs-xpcs.h for that reason (for the sja1105driver to be able to use it in a later patch).Signed-off-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Fri, 11 Jun 2021 20:05:25 +0000</pubDate>
        <dc:creator>Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;</dc:creator>
    </item>
<item>
        <title>0da4c3d3 - net: phy: add Lynx PCS module</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#0da4c3d3</link>
        <description>net: phy: add Lynx PCS moduleAdd a Lynx PCS module which exposes the necessary operations to drivethe PCS using phylink.The majority of the code is extracted from the Felix DSA driver, whichwill be also modified in a later patch, and exposed as a separate modulefor code reusability purposes.As such, this aims at feature and bug parity with the existing Felix DSAdriver, and thus USXGMII, SGMII, QSGMII and 2500Base-X (only w/o in-bandAN) are supported by the Lynx PCS module since these were also supportedby Felix.The module can only be enabled by the drivers in need and not userselectable.Signed-off-by: Ioana Ciornei &lt;ioana.ciornei@nxp.com&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Sun, 30 Aug 2020 08:34:01 +0000</pubDate>
        <dc:creator>Ioana Ciornei &lt;ioana.ciornei@nxp.com&gt;</dc:creator>
    </item>
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        <title>2fa4e4b7 - net: pcs: Move XPCS into new PCS subdirectory</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/net/pcs/Makefile#2fa4e4b7</link>
        <description>net: pcs: Move XPCS into new PCS subdirectoryCreate drivers/net/pcs and move the Synopsys DesignWare XPCS into thenew directory. Move the header file into a subdirectoryinclude/linux/pcsStart a naming convention of all PCS files use the prefix pcs-, andrename the XPCS files to fit.v2:Add include/linux/pcsv4:Fix include path in stmmac.Remove PCS_DEVICES to avoid new promptsCc: Jose Abreu &lt;Jose.Abreu@synopsys.com&gt;Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;

            List of files:
            /linux-6.15/drivers/net/pcs/Makefile</description>
        <pubDate>Thu, 27 Aug 2020 02:00:28 +0000</pubDate>
        <dc:creator>Andrew Lunn &lt;andrew@lunn.ch&gt;</dc:creator>
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