5de15b61 - mtd: hyperbus: add Renesas RPC-IF driver

Sat, 03 Oct 2020 20:23:20 +0000

mtd: hyperbus: add Renesas RPC-IF driverAdd the HyperFLash driver for the Renesas RPC-IF. It's the "front end"driver using the "back end" APIs in the main driver to talk to the realhardware.Signed-off-by: Sergei Shtylyov Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/78abb851-2beb-fe7d-87e5-ce58ee877d35@gmail.com List of files: /linux-6.15/drivers/mtd/hyperbus/Makefile

b07079f1 - mtd: hyperbus: Add driver for TI's HyperBus memory controller

Tue, 25 Jun 2019 07:57:46 +0000

mtd: hyperbus: Add driver for TI's HyperBus memory controllerAdd driver for HyperBus memory controller on TI's AM654 SoC. ProgrammingIP is pretty simple and provides direct memory mapped access toconnected Flash devices.Add basic support for the IP without DMA. Second chip-select is notsupported for now.Signed-off-by: Vignesh Raghavendra Signed-off-by: Miquel Raynal List of files: /linux-6.15/drivers/mtd/hyperbus/Makefile

dcc7d344 - mtd: Add support for HyperBus memory devices

Tue, 25 Jun 2019 07:57:44 +0000

mtd: Add support for HyperBus memory devicesCypress' HyperBus is Low Signal Count, High Performance Double Data RateBus interface between a host system master and one or more slaveinterfaces. HyperBus is used to connect microprocessor, microcontroller,or ASIC devices with random access NOR flash memory (called HyperFlash)or self refresh DRAM (called HyperRAM).Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS)signal and either Single-ended clock(3.0V parts) or Differential clock(1.8V parts). It uses ChipSelect lines to select b/w multiple slaves.At bus level, it follows a separate protocol described in HyperBusspecification[1].HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similarto that of existing parallel NORs. Since HyperBus is x8 DDR bus,its equivalent to x16 parallel NOR flash with respect to bits per clockcycle. But HyperBus operates at >166MHz frequencies.HyperRAM provides direct random read/write access to flash memoryarray.But, HyperBus memory controllers seem to abstract implementation detailsand expose a simple MMIO interface to access connected flash.Add support for registering HyperFlash devices with MTD framework. MTDmaps framework along with CFI chip support framework are used to supportcommunicating with flash.Framework is modelled along the lines of spi-nor framework. HyperBusmemory controller (HBMC) drivers calls hyperbus_register_device() toregister a single HyperFlash device. HyperFlash core parses MMIO accessinformation from DT, sets up the map_info struct, probes CFI flash andregisters it with MTD framework.Some HBMC masters need calibration/training sequence[3] to be carriedout, in order for DLL inside the controller to lock, by reading a knownstring/pattern. This is done by repeatedly reading CFI QueryIdentification String. Calibration needs to be done before trying to detectflash as part of CFI flash probe.HyperRAM is not supported at the moment.HyperBus specification can be found at[1]HyperFlash datasheet can be found at[2][1] https://www.cypress.com/file/213356/download[2] https://www.cypress.com/file/213346/download[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf Table 12-5741. HyperFlash Access SequenceSigned-off-by: Vignesh Raghavendra Signed-off-by: Miquel Raynal List of files: /linux-6.15/drivers/mtd/hyperbus/Makefile

Changes in Makefile

5de15b61 - mtd: hyperbus: add Renesas RPC-IF driver

b07079f1 - mtd: hyperbus: Add driver for TI's HyperBus memory controller

dcc7d344 - mtd: Add support for HyperBus memory devices