Changes in Makefile

c6674154 - irqchip: Add the Sophgo SG2042 MSI interrupt controller

Wed, 26 Feb 2025 02:15:19 +0000

irqchip: Add the Sophgo SG2042 MSI interrupt controllerAdd driver for Sophgo SG2042 MSI interrupt controller.Signed-off-by: Chen Wang Signed-off-by: Thomas Gleixner Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/all/3104216ca90a5f532bafb676c1c5b1efb19e94d1.1740535748.git.unicorn_wang@outlook.com List of files: /linux-6.15/drivers/irqchip/Makefile

32c6c054 - irqchip: Add Broadcom BCM2712 MSI-X interrupt controller

Mon, 24 Feb 2025 08:35:55 +0000

irqchip: Add Broadcom BCM2712 MSI-X interrupt controllerAdd an interrupt controller driver for MSI-X Interrupt Peripheral (MIP)hardware block found in BCM2712. The interrupt controller is used tohandle MSI-X interrupts from peripherials behind PCIe endpoints likeRPi1 south bridge found in RPi5.There are two MIPs on BCM2712, the first has 64 consecutive SPIsassigned to 64 output vectors, and the second has 17 SPIs, but only8 of them are consecutive starting at the 8th output vector.Signed-off-by: Stanimir Varbanov Reviewed-by: Thomas Gleixner Tested-by: Ivan T. Ivanov Link: https://lore.kernel.org/r/20250224083559.47645-4-svarbanov@suse.de[kwilczynski: commit log]Signed-off-by: Krzysztof Wilczyński List of files: /linux-6.15/drivers/irqchip/Makefile

25caea95 - irqchip: Add T-HEAD C900 ACLINT SSWI driver

Thu, 31 Oct 2024 06:08:58 +0000

irqchip: Add T-HEAD C900 ACLINT SSWI driverAdd a driver for the T-HEAD C900 ACLINT SSWI device. This device allowsthe system with T-HEAD cpus to send ipi via fast device interface.Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241031060859.722258-3-inochiama@gmail.com List of files: /linux-6.15/drivers/irqchip/Makefile

010863f4 - irqchip/aspeed-intc: Add AST27XX INTC support

Wed, 16 Oct 2024 02:24:10 +0000

irqchip/aspeed-intc: Add AST27XX INTC supportSupport Aspeed Interrupt Controller on Aspeed Silicon SoCs.ASPEED interrupt controller(INTC) maps the internal interruptsources to a parent interrupt controller, which can be GIC or INTC.Signed-off-by: Kevin Chen Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241016022410.1154574-3-kevin_chen@aspeedtech.com List of files: /linux-6.15/drivers/irqchip/Makefile

0d7605e7 - irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver

Wed, 09 Oct 2024 23:08:16 +0000

irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driverAdd driver for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU).This driver supports the external interrupts NMI, IRQn, and TINTn.Signed-off-by: Fabrizio Castro Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241009230817.798582-3-fabrizio.castro.jz@renesas.com List of files: /linux-6.15/drivers/irqchip/Makefile

ae16f05c - irqchip/loongarch-avec: Add AVEC irqchip support

Fri, 23 Aug 2024 10:43:37 +0000

irqchip/loongarch-avec: Add AVEC irqchip supportIntroduce the advanced extended interrupt controllers (AVECINTC). Thisfeature will allow each core to have 256 independent interrupt vectorsand MSI interrupts can be independently routed to any vector on any CPU.The whole topology of irqchips in LoongArch machines looks like this ifAVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+Co-developed-by: Jianmin Lv Signed-off-by: Jianmin Lv Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Signed-off-by: Tianyang Zhang Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20240823104337.25577-2-zhangtianyang@loongson.cn List of files: /linux-6.15/drivers/irqchip/Makefile

7f2baef0 - irqchip/gic-v3-its: Switch platform MSI to MSI parent

Sun, 23 Jun 2024 15:18:46 +0000

irqchip/gic-v3-its: Switch platform MSI to MSI parentSimilar to the previous conversion of the PCI/MSI support lift theprepare() callback from the existing platform MSI code and enableplatform MSI and the related device domain bus tokens in selectand the child domain initialization code.All platform MSI users are automatically using the new per device MSI modelnow.Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142235.271734124@linutronix.de List of files: /linux-6.15/drivers/irqchip/Makefile

b5712bf8 - irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X]

Sun, 23 Jun 2024 15:18:39 +0000

irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X]The its_pci_msi_prepare() function from the ITS-PCI/MSI code provides the'global' PCI/MSI domains. Move this function to the ITS-MSI parent code andamend the function to use the domain hardware size, which is the MSI[X]vector count, for allocating the ITS slots for the PCI device.Enable PCI matching in msi_parent_ops and provide the necessary update tothe ITS specific child domain initialization function so that the preparecallback gets invoked on allocations.The latter might be optimized to do the allocation right at the point wherethe child domain is initialized, but keep it simple for now.Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142235.024567623@linutronix.de List of files: /linux-6.15/drivers/irqchip/Makefile

48f71d56 - irqchip/gic-v3-its: Provide MSI parent infrastructure

Sun, 23 Jun 2024 15:18:36 +0000

irqchip/gic-v3-its: Provide MSI parent infrastructureTo support per device MSI domains the ITS must provide MSI parent domainfunctionality.Provide the basic skeleton for this: - msi_parent_ops - child domain init callback - the MSI parent flag set in irqdomain::flagsThis does not make ITS a functional parent domain as there is no bit set inthe bus_select_mask yet, but it provides the base to implement PCI andplatform MSI support gradually on top.Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142234.903076277@linutronix.de List of files: /linux-6.15/drivers/irqchip/Makefile

72e257c6 - irqchip: Provide irq-msi-lib

Sun, 23 Jun 2024 15:18:34 +0000

irqchip: Provide irq-msi-libAll irqdomains which provide MSI parent domain functionality for per deviceMSI domains need to provide a select() callback for the irqdomain and afunction to initialize the child domain.Most of these functions would just be copy&paste with minimalmodifications, so provide a library function which implements the requiredfunctionality and is customizable via parent_domain::msi_parent_ops. Thecheck for the supported bus tokens in msi_lib_init_dev_msi_info() isexpanded step by step within the next patches.Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142234.840975799@linutronix.de List of files: /linux-6.15/drivers/irqchip/Makefile

18db1b6d - Revert "Loongarch: Support loongarch avec"

Tue, 25 Jun 2024 05:40:08 +0000

Revert "Loongarch: Support loongarch avec"This reverts commit 760d7e719499d64beea62bfcf53938fb233bb6e7.This results in build failures and has other issues according to Tianyang.Reported-by: kernel test robot Signed-off-by: Thomas Gleixner Cc: Tianyang Zhang Closes: https://lore.kernel.org/oe-kbuild-all/202406240451.ygBFNyJ3-lkp@intel.com/ List of files: /linux-6.15/drivers/irqchip/Makefile

350755e2 - irqchip/stm32-exti: Split MCU and MPU code

Thu, 20 Jun 2024 08:31:11 +0000

irqchip/stm32-exti: Split MCU and MPU codeKeep only the code for ARMv7m STM32 MCUs in in stm32-exti.c and split outthe code for ARMv7a & ARMv8a STM32MPxxx MPUs into stm32mp-exti.cSigned-off-by: Antonio Borneo Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240620083115.204362-5-antonio.borneo@foss.st.com List of files: /linux-6.15/drivers/irqchip/Makefile

760d7e71 - Loongarch: Support loongarch avec

Tue, 04 Jun 2024 12:50:26 +0000

Loongarch: Support loongarch avecIntroduce the advanced extended interrupt controllers. This feature willallow each core to have 256 independent interrupt vectors and MSIinterrupts can be independently routed to any vector on any CPU.[ tglx: Fixed up coding style. Made on/offline functions void ]Co-developed-by: Jianmin Lv Signed-off-by: Jianmin Lv Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Signed-off-by: Tianyang Zhang Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240604125026.18745-1-zhangtianyang@loongson.cn List of files: /linux-6.15/drivers/irqchip/Makefile

3e3a7b35 - irqchip: Add support for LAN966x OIC

Fri, 14 Jun 2024 17:32:23 +0000

irqchip: Add support for LAN966x OICThe Microchip LAN966x outband interrupt controller (OIC) maps theinternal interrupt sources of the LAN966x device to an externalinterrupt.When the LAN966x device is used as a PCI device, the external interruptis routed to the PCI interrupt.Signed-off-by: Herve Codina Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240614173232.1184015-23-herve.codina@bootlin.com List of files: /linux-6.15/drivers/irqchip/Makefile

ca8df97f - irqchip/riscv-aplic: Add support for MSI-mode

Thu, 07 Mar 2024 14:03:05 +0000

irqchip/riscv-aplic: Add support for MSI-modeThe RISC-V advanced platform-level interrupt controller (APLIC) hastwo modes of operation: 1) Direct mode and 2) MSI mode.(For more details, refer https://github.com/riscv/riscv-aia)In APLIC MSI-mode, wired interrupts are forwared as message signaledinterrupts (MSIs) to CPUs via IMSIC.Extend the existing APLIC irqchip driver to support MSI-mode forRISC-V platforms having both wired interrupts and MSIs.Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Tested-by: Björn Töpel Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20240307140307.646078-8-apatel@ventanamicro.com List of files: /linux-6.15/drivers/irqchip/Makefile

2333df5a - irqchip: Add RISC-V advanced PLIC driver for direct-mode

Thu, 07 Mar 2024 14:03:04 +0000

irqchip: Add RISC-V advanced PLIC driver for direct-modeThe RISC-V advanced interrupt architecture (AIA) specification definesadvanced platform-level interrupt controller (APLIC) which has two modesof operation: 1) Direct mode and 2) MSI mode.(For more details, refer https://github.com/riscv/riscv-aia)In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs)as a local external interrupt.Add a platform irqchip driver for the RISC-V APLIC direct-mode tosupport RISC-V platforms having only wired interrupts.Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Tested-by: Björn Töpel Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20240307140307.646078-7-apatel@ventanamicro.com List of files: /linux-6.15/drivers/irqchip/Makefile

027e125a - irqchip/riscv-imsic: Add device MSI domain support for platform devices

Thu, 07 Mar 2024 14:03:01 +0000

irqchip/riscv-imsic: Add device MSI domain support for platform devicesThe Linux platform MSI support allows per-device MSI domains so adda platform irqchip driver for RISC-V IMSIC which provides a base IRQdomain with MSI parent support for platform device domains.The IMSIC platform driver assumes that the IMSIC state is alreadyinitialized by the IMSIC early driver.Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Tested-by: Björn Töpel Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20240307140307.646078-4-apatel@ventanamicro.com List of files: /linux-6.15/drivers/irqchip/Makefile

21a8f8a0 - irqchip: Add RISC-V incoming MSI controller early driver

Thu, 07 Mar 2024 14:03:00 +0000

irqchip: Add RISC-V incoming MSI controller early driverThe RISC-V advanced interrupt architecture (AIA) specificationdefines a new MSI controller called incoming message signalledinterrupt controller (IMSIC) which manages MSI on per-HART (orper-CPU) basis. It also supports IPIs as software injected MSIs.(For more details refer https://github.com/riscv/riscv-aia)Add an early irqchip driver for RISC-V IMSIC which sets up theIMSIC state and provide IPIs.Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Tested-by: Björn Töpel Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20240307140307.646078-3-apatel@ventanamicro.com List of files: /linux-6.15/drivers/irqchip/Makefile

e4e53503 - irqchip: Add StarFive external interrupt controller

Mon, 26 Feb 2024 05:50:25 +0000

irqchip: Add StarFive external interrupt controllerAdd StarFive external interrupt controller for JH8100 SoC.Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Reviewed-by: Ley Foon Tan Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20240226055025.1669223-3-changhuang.liang@starfivetech.com List of files: /linux-6.15/drivers/irqchip/Makefile

fa8dede4 - irqchip: remove davinci aintc driver

Fri, 30 Sep 2022 13:39:51 +0000

irqchip: remove davinci aintc driverThe aintc driver was used on Davinci DM3xx and DM64xx SoCs, all ofwhich got dropped from Linux, so this driver is orphaned as well.Acked-by: Bartosz Golaszewski Acked-by: Marc Zyngier Signed-off-by: Arnd Bergmann List of files: /linux-6.15/drivers/irqchip/Makefile