Changes in Kconfig

104712a0 - fpga: xilinx-selectmap: add new driver

Thu, 21 Mar 2024 22:04:35 +0000

fpga: xilinx-selectmap: add new driverXilinx 7 series FPGA can be programmed using a parallel port namedthe SelectMAP interface in the datasheet. This interface is compatiblewith the i.MX6 EIM bus controller but other types of external memorymapped parallel bus might work.xilinx-selectmap currently only supports the x8 mode where data is loadedat one byte per rising edge of the clock, with the MSb of each bytepresented to the D0 pin.Signed-off-by: Charles Perry [yilun.xu@linux.intel.com: replace data type of i from u32 to size_t]Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

a52e3a9d - fpga: xilinx-spi: extract a common driver core

Thu, 21 Mar 2024 22:04:33 +0000

fpga: xilinx-spi: extract a common driver coreFactor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE)protocol in xilinx-core so that it can be reused for another driver.This commit does not change anything functionally to xilinx-spi.xilinx-core expects drivers to provide a write(const char* buf,size_t count) function that performs the actual write to the device,as well as a struct device* for resource management.Signed-off-by: Charles Perry Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-2-charles.perry@savoirfairelinux.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

3969f645 - fpga: add configuration for the FPGA KUnit test suites.

Tue, 18 Jul 2023 13:03:04 +0000

fpga: add configuration for the FPGA KUnit test suites.Add configuration for the KUnit test suites for the core componentsof the FPGA subsystem.Signed-off-by: Marco Pagani Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20230718130304.87048-5-marpagan@redhat.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

603aed8f - mfd: intel-m10-bmc: Split into core and spi specific parts

Mon, 16 Jan 2023 10:08:38 +0000

mfd: intel-m10-bmc: Split into core and spi specific partsSplit the common code from intel-m10-bmc driver into intel-m10-bmc-coreand move the SPI bus parts into an interface specific file.intel-m10-bmc-core becomes the core MFD functions which can supportmultiple bus interface like SPI bus.Co-developed-by: Tianfei zhang Signed-off-by: Tianfei zhang Reviewed-by: Russ Weight Acked-by: Guenter Roeck # hwmonReviewed-by: Xu Yilun Signed-off-by: Ilpo Järvinen Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20230116100845.6153-5-ilpo.jarvinen@linux.intel.com List of files: /linux-6.15/drivers/fpga/Kconfig

dfd10332 - fpga: m10bmc-sec: Fix kconfig dependencies

Tue, 15 Nov 2022 00:11:27 +0000

fpga: m10bmc-sec: Fix kconfig dependenciesThe secure update driver depends on the firmware-upload functionality ofthe firmware-loader. The firmware-loader is carried in the firmware-classdriver which is enabled with the tristate CONFIG_FW_LOADER option. Thefirmware-upload functionality is included in the firmware-class driver ifthe bool FW_UPLOAD config is set.The current dependency statement, "depends on FW_UPLOAD", is not adequatebecause it does not implicitly turn on FW_LOADER. Instead of adding adependency, follow the convention used by drivers that require theFW_LOADER_USER_HELPER functionality of the firmware-loader by usingselect for both FW_LOADER and FW_UPLOAD.Fixes: bdf86d0e6ca3 ("fpga: m10bmc-sec: create max10 bmc secure update")Reported-by: kernel test robot Cc: stable@vger.kernel.orgSigned-off-by: Russ Weight Acked-by: Randy Dunlap Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20221115001127.289890-1-russell.h.weight@intel.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

463dd43b - fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager

Tue, 25 Oct 2022 05:39:46 +0000

fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA managerAdd support to the FPGA manager for programming Lattice ECP5 FPGA overslave SPI sysCONFIG interface.sysCONFIG interface core functionality is separate from both ECP5 andSPI specifics, so support for other FPGAs with different port types canbe added in the future.Signed-off-by: Ivan Bornyakov Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20221025053947.2737-2-i.bornyakov@metrotek.ru[yilun.xu@intel.com: remove redundant blank line after kmemdup]Signed-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

5f8d4a90 - fpga: microchip-spi: add Microchip MPF FPGA manager

Thu, 23 Jun 2022 16:32:46 +0000

fpga: microchip-spi: add Microchip MPF FPGA managerAdd support to the FPGA manager for programming Microchip PolarfireFPGAs over slave SPI interface with .dat formatted bitsream image.Signed-off-by: Ivan Bornyakov Reviewed-by: Conor Dooley Tested-by: Conor Dooley Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ruSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

bdf86d0e - fpga: m10bmc-sec: create max10 bmc secure update

Mon, 06 Jun 2022 16:00:35 +0000

fpga: m10bmc-sec: create max10 bmc secure updateCreate a sub-driver for the FPGA Card BMC in order to support secureupdates. This patch creates the Max10 BMC Secure Update driver andprovides sysfs files for displaying the root entry hashes (REH) for theFPGA static region (SR), the FPGA Partial Reconfiguration (PR) region,and the card BMC.The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmwareand FPGA images are authenticated using ECDSA before loading and executingon the card. Code Signing Keys (CSK) are used to sign images. CSKs aresigned by a root key. The root entry hash is created from the root publickey.The RoT provides authentication by storing an REH bitstream to a write-oncelocation. Image signatures are verified against the hash.Reviewed-by: Tom Rix Tested-by: Tianfei Zhang Signed-off-by: Russ Weight Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Kconfig

5f1895e0 - fpga: Fix spelling mistake "eXchnage" -> "exchange" in Kconfig

Wed, 28 Jul 2021 21:51:50 +0000

fpga: Fix spelling mistake "eXchnage" -> "exchange" in KconfigThere is a spelling mistake in the Kconfig text. Fix it.Reviewed-by: Tom Rix Signed-off-by: Colin Ian King Signed-off-by: Moritz Fischer List of files: /linux-6.15/drivers/fpga/Kconfig

01c54e62 - fpga: versal-fpga: Add versal fpga manager driver

Sat, 26 Jun 2021 15:52:48 +0000

fpga: versal-fpga: Add versal fpga manager driverAdd support for Xilinx Versal FPGA manager.PDI source type can be DDR, OCM, QSPI flash etc..But driver allocates memory always from DDR, Since driver supports onlyDDR source type.Reviewed-by: Moritz Fischer Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20210626155248.5004-6-nava.manne@xilinx.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

df82d2ec - fpga: change FPGA indirect article to an

Tue, 08 Jun 2021 21:23:44 +0000

fpga: change FPGA indirect article to anChange use of 'a fpga' to 'an fpga'Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20210608212350.3029742-7-trix@redhat.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

30a2ac9a - fpga: Add support for Xilinx DFX AXI Shutdown manager

Thu, 11 Feb 2021 05:11:48 +0000

fpga: Add support for Xilinx DFX AXI Shutdown managerThis patch adds support for Xilinx Dynamic Function eXchange(DFX) AXIshutdown manager IP. It can be used to safely handling the AXI trafficon a Reconfigurable Partition when it is undergoing dynamic reconfigurationand there by preventing system deadlock that may occur if AXI transactionsare interrupted during reconfiguration.PR-Decoupler and AXI shutdown manager are completely different IPs.But both the IP registers are compatible and also both belong to thesame sub-system (fpga-bridge).So using same driver for both IP's.Signed-off-by: Nava kishore Manne Reviewed-by: Tom Rix Signed-off-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

3a1fef70 - fpga: altera: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs

Thu, 11 Mar 2021 15:27:35 +0000

fpga: altera: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCsARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the32-bit ARM drivers to rely on new symbol.Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen List of files: /linux-6.15/drivers/fpga/Kconfig

4a9a1a56 - arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGA

Thu, 11 Mar 2021 15:25:38 +0000

arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGAAgilex, N5X and Stratix 10 share all quite similar arm64 hard cores andSoC-part. Up to a point that N5X uses the same DTSI as Agilex. Fromthe Linux kernel point of view these are flavors of the samearchitecture so there is no need for three top-level arm64architectures. Simplify this by merging all three architectures intoARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries.The side effect is that the INTEL_STRATIX10_SERVICE will now beavailable for both 32-bit and 64-bit Intel SoCFPGA, even though it isused only for 64-bit.Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen List of files: /linux-6.15/drivers/fpga/Kconfig

6f1e376c - fpga: Add support for Xilinx DFX AXI Shutdown manager

Thu, 11 Feb 2021 05:11:48 +0000

56172ab3 - fpga: dfl: add support for N3000 Nios private feature

Thu, 07 Jan 2021 04:37:13 +0000

fpga: dfl: add support for N3000 Nios private featureThis patch adds support for the Nios handshake private feature on IntelPAC (Programmable Acceleration Card) N3000.The Nios is the embedded processor on the FPGA card. This private featureprovides a handshake interface to FPGA Nios firmware, which receivesretimer configuration command from host and executes via an internal SPImaster (spi-altera). When Nios finishes the configuration, host takes overthe ownership of the SPI master to control an Intel MAX10 BMC (BoardManagement Controller) Chip on the SPI bus.For Nios firmware handshake part, this driver requests the retimerconfiguration for Nios firmware on probe, and adds some sysfs nodes foruser to query the onboard retimer's working mode and Nios firmwareversion.For SPI part, this driver adds a spi-altera platform device as well asthe MAX10 BMC spi slave info. A spi-altera driver will be matched tohandle the following SPI work.[mdf@kernel.org: Fixed up ABI doc kernel release]Reviewed-by: Tom Rix Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Signed-off-by: YueHaibing Link: https://lore.kernel.org/r/20210107043714.991646-8-mdf@kernel.orgSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

1a16af33 - fpga: Specify HAS_IOMEM dependency for FPGA_DFL

Sun, 22 Nov 2020 00:15:49 +0000

fpga: Specify HAS_IOMEM dependency for FPGA_DFLBecause dfl.c uses the 'devm_ioremap', 'devm_iounmap','devm_ioremap_resource', and 'devm_platform_ioremap_resource'functions, it should depend on HAS_IOMEM.This fixes make allyesconfig under UML (ARCH=um), which doesn't provideHAS_IOMEM.[mdf@kernel.org: Removed "drivers: " in commit message]Fixes: 89eb35e810a8 ("fpga: dfl: map feature mmio resources in their own feature drivers")Signed-off-by: David Gow Signed-off-by: Moritz Fischer Link: https://lore.kernel.org/r/20201122001549.107023-2-mdf@kernel.orgSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

6a47d6ef - fpga: zynqmp: fix modular build

Tue, 05 May 2020 14:00:11 +0000

fpga: zynqmp: fix modular buildTwo symbols need to be exported to allow the zynqmp-fpga moduleto get loaded dynamically:ERROR: modpost: "zynqmp_pm_fpga_load" [drivers/fpga/zynqmp-fpga.ko] undefined!ERROR: modpost: "zynqmp_pm_fpga_get_status" [drivers/fpga/zynqmp-fpga.ko] undefined!To ensure this is done correctly, also fix the Kconfig dependencyto only allow building the fpga driver when the firmware driver iseither disabled, or when it is reachable. With that, the dependencyon the SoC itself can be removed, and there are no surprises whenthe fpga driver is built-in but the firmware a module.Fixes: 4db8180ffe7c ("firmware: xilinx: Remove eemi ops for fpga related APIs")Signed-off-by: Arnd Bergmann Signed-off-by: Moritz Fischer List of files: /linux-6.15/drivers/fpga/Kconfig

724142f8 - fpga: dfl: fme: add performance reporting support

Mon, 27 Apr 2020 01:06:23 +0000

fpga: dfl: fme: add performance reporting supportThis patch adds support for performance reporting private featurefor FPGA Management Engine (FME). Now it supports several differentperformance counters, including 'basic', 'cache', 'fabric', 'vtd'and 'vtd_sip'. It allows user to use standard linux tools to accessthese performance counters.e.g. List all events by "perf list" perf list | grep fme dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ... dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ... dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ... dfl_fme0/clock [Kernel PMU event] ...e.g. check increased counter value after run one application using"perf stat" command. perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test Performance counter stats for './test': 1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/ 1.009496520 seconds time elapsedPlease note that fabric counters support both fab_* and fab_port_*, butactually they are sharing one set of performance counters in hardware.If user wants to monitor overall data events on fab_* then fab_port_*can't be supported at the same time, see example below:perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/ Performance counter stats for 'system wide': 0 dfl_fme0/fab_mmio_read/ dfl_fme0/fab_port_mmio_write,portid=0/ 2.141064085 seconds time elapsedSigned-off-by: Luwei Kang Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Kconfig

4284c65a - fpga: dfl: fme: add thermal management support

Mon, 14 Oct 2019 05:42:02 +0000

fpga: dfl: fme: add thermal management supportThis patch adds support to thermal management private feature for DFLFPGA Management Engine (FME). This private feature driver registersa hwmon for thermal/temperature monitoring (hwmon temp1_input).If hardware automatic throttling is supported by this hardware, thendriver also exposes sysfs interfaces under hwmon for thresholds(temp1_max/ crit/ emergency), threshold alarms (temp1_max_alarm/temp1_crit_alarm) and throttling policy (temp1_max_policy).Signed-off-by: Luwei Kang Signed-off-by: Russ Weight Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Acked-by: Guenter Roeck Reviewed-by: Moritz Fischer Signed-off-by: Moritz Fischer List of files: /linux-6.15/drivers/fpga/Kconfig