Changes in Makefile

353d5c24 - dmaengine: dw-edma: Add HDMA DebugFS support

Sat, 20 May 2023 05:08:52 +0000

dmaengine: dw-edma: Add HDMA DebugFS supportAdd HDMA DebugFS support to show registers contentSigned-off-by: Cai Huoqing Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Serge Semin Link: https://lore.kernel.org/r/20230520050854.73160-5-cai.huoqing@linux.devSigned-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile

e74c3957 - dmaengine: dw-edma: Add support for native HDMA

Sat, 20 May 2023 05:08:51 +0000

dmaengine: dw-edma: Add support for native HDMAAdd support for HDMA NATIVE, as long the IP design has setthe compatible register map parameter-HDMA_NATIVE,which allows compatibility for native HDMA register configuration.The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.And the native HDMA registers are different from eDMA, so this patchadd support for HDMA NATIVE mode.HDMA write and read channels operate independently to maximizethe performance of the HDMA read and write data transfer overthe link When you configure the HDMA with multiple read channels,then it uses a round robin (RR) arbitration scheme to selectthe next read channel to be serviced.The same applies when youhave multiple write channels.The native HDMA driver also supports a maximum of 16 independentchannels (8 write + 8 read), which can run simultaneously.Both SAR (Source Address Register) and DAR (Destination Address Register)are aligned to byte.Signed-off-by: Cai Huoqing Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Serge Semin Link: https://lore.kernel.org/r/20230520050854.73160-4-cai.huoqing@linux.devSigned-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile

41aaff2a - dmaengine: Add Synopsys eDMA IP PCIe glue-logic

Tue, 04 Jun 2019 13:29:26 +0000

dmaengine: Add Synopsys eDMA IP PCIe glue-logicSynopsys eDMA IP is normally distributed along with Synopsys PCIeEndPoint IP (depends of the use and licensing agreement).This IP requires some basic configurations, such as: - eDMA registers BAR - eDMA registers offset - eDMA registers size - eDMA linked list memory BAR - eDMA linked list memory offset - eDMA linked list memory size - eDMA data memory BAR - eDMA data memory offset - eDMA data memory size - eDMA version - eDMA mode - IRQs available for eDMAAs a working example, PCIe glue-logic will attach to a Synopsys PCIeEndPoint IP prototype kit (Vendor ID = 0x16c3, Device ID = 0xedda),which has built-in an eDMA IP with this default configuration: - eDMA registers BAR = 0 - eDMA registers offset = 0x00001000 (4 Kbytes) - eDMA registers size = 0x00002000 (8 Kbytes) - eDMA linked list memory BAR = 2 - eDMA linked list memory offset = 0x00000000 (0 Kbytes) - eDMA linked list memory size = 0x00800000 (8 Mbytes) - eDMA data memory BAR = 2 - eDMA data memory offset = 0x00800000 (8 Mbytes) - eDMA data memory size = 0x03800000 (56 Mbytes) - eDMA version = 0 - eDMA mode = EDMA_MODE_UNROLL - IRQs = 1This driver can be compile as built-in or external module in kernel.To enable this driver just select DW_EDMA_PCIE option in kernelconfiguration, however it requires and selects automatically DW_EDMAoption too.Signed-off-by: Gustavo Pimentel Cc: Vinod Koul Cc: Dan Williams Cc: Russell King Cc: Lorenzo Pieralisi Cc: Joao Pinto Signed-off-by: Gustavo Pimentel Signed-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile

305aebef - dmaengine: Add Synopsys eDMA IP version 0 debugfs support

Tue, 04 Jun 2019 13:29:24 +0000

dmaengine: Add Synopsys eDMA IP version 0 debugfs supportAdd Synopsys eDMA IP version 0 debugfs support to assist any debugin the future.Creates a file system structure composed by folders and files that mimicthe IP register map (this files are read only) to ease any debug.To enable this feature is necessary to select DEBUG_FS option on kernelconfiguration.Small output example:(eDMA IP version 0, unroll, 1 write + 1 read channels)% mount -t debugfs none /sys/kernel/debug/% tree /sys/kernel/debug/dw-edma-core:0/dw-edma/├── version├── mode├── wr_ch_cnt├── rd_ch_cnt└── registers ├── ctrl_data_arb_prior ├── ctrl ├── write │ ├── engine_en │ ├── doorbell │ ├── ch_arb_weight_low │ ├── ch_arb_weight_high │ ├── int_status │ ├── int_mask │ ├── int_clear │ ├── err_status │ ├── done_imwr_low │ ├── done_imwr_high │ ├── abort_imwr_low │ ├── abort_imwr_high │ ├── ch01_imwr_data │ ├── ch23_imwr_data │ ├── ch45_imwr_data │ ├── ch67_imwr_data │ ├── linked_list_err_en │ ├── engine_chgroup │ ├── engine_hshake_cnt_low │ ├── engine_hshake_cnt_high │ ├── ch0_pwr_en │ ├── ch1_pwr_en │ ├── ch2_pwr_en │ ├── ch3_pwr_en │ ├── ch4_pwr_en │ ├── ch5_pwr_en │ ├── ch6_pwr_en │ ├── ch7_pwr_en │ └── channel:0 │ ├── ch_control1 │ ├── ch_control2 │ ├── transfer_size │ ├── sar_low │ ├── sar_high │ ├── dar_high │ ├── llp_low │ └── llp_high └── read ├── engine_en ├── doorbell ├── ch_arb_weight_low ├── ch_arb_weight_high ├── int_status ├── int_mask ├── int_clear ├── err_status_low ├── err_status_high ├── done_imwr_low ├── done_imwr_high ├── abort_imwr_low ├── abort_imwr_high ├── ch01_imwr_data ├── ch23_imwr_data ├── ch45_imwr_data ├── ch67_imwr_data ├── linked_list_err_en ├── engine_chgroup ├── engine_hshake_cnt_low ├── engine_hshake_cnt_high ├── ch0_pwr_en ├── ch1_pwr_en ├── ch2_pwr_en ├── ch3_pwr_en ├── ch4_pwr_en ├── ch5_pwr_en ├── ch6_pwr_en ├── ch7_pwr_en └── channel:0 ├── ch_control1 ├── ch_control2 ├── transfer_size ├── sar_low ├── sar_high ├── dar_high ├── llp_low └── llp_highSigned-off-by: Gustavo Pimentel Cc: Vinod Koul Cc: Dan Williams Cc: Andy Shevchenko Cc: Russell King Cc: Joao Pinto Signed-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile

7e4b8a4f - dmaengine: Add Synopsys eDMA IP version 0 support

Tue, 04 Jun 2019 13:29:23 +0000

dmaengine: Add Synopsys eDMA IP version 0 supportAdd support for the eDMA IP version 0 driver for both register maps (legacyand unroll).The legacy register mapping was the initial implementation, which consistedin having all registers belonging to channels multiplexed, which could bechange anytime (which could led a race-condition) by view port register(access to only one channel available each time).This register mapping is not very effective and efficient in a multithreadenvironment, which has led to the development of unroll registers mapping,which consists of having all channels registers accessible any time byspreading all channels registers by an offset between them.This version supports a maximum of 16 independent channels (8 write +8 read), which can run simultaneously.Implements a scatter-gather transfer through a linked list, where the sizeof linked list depends on the allocated memory divided equally among allchannels.Each linked list descriptor can transfer from 1 byte to 4 Gbytes and isalignmented to DWORD.Both SAR (Source Address Register) and DAR (Destination Address Register)are alignmented to byte.Signed-off-by: Gustavo Pimentel Cc: Vinod Koul Cc: Dan Williams Cc: Andy Shevchenko Cc: Russell King Cc: Joao Pinto Signed-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile

e63d79d1 - dmaengine: Add Synopsys eDMA IP core driver

Tue, 04 Jun 2019 13:29:22 +0000

dmaengine: Add Synopsys eDMA IP core driverAdd Synopsys PCIe Endpoint eDMA IP core driver to kernel.This IP is generally distributed with Synopsys PCIe Endpoint IP (dependsof the use and licensing agreement).This core driver, initializes and configures the eDMA IP using vma-helpersfunctions and dma-engine subsystem.This driver can be compile as built-in or external module in kernel.To enable this driver just select DW_EDMA option in kernel configuration,however it requires and selects automatically DMA_ENGINE andDMA_VIRTUAL_CHANNELS option too.In order to transfer data from point A to B as fast as possible this IPrequires a dedicated memory space containing linked list of elements.All elements of this linked list are continuous and each one describes adata transfer (source and destination addresses, length and a controlvariable).For the sake of simplicity, lets assume a memory space for channel write0 which allows about 42 elements.+---------+| Desc #0 |-++---------+ | V +----------+ | Chunk #0 |-+ | CB = 1 | | +----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp | | +----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #1 |-+ | CB = 0 | | +-----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp | | +-----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #2 |-+ | CB = 1 | | +-----------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp | | +-----------+ +-----+ +------------+ +-----+ V +----------+ | Chunk #3 |-+ | CB = 0 | | +------------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp | +------------+ +-----+ +------------+ +-----+Legend: - Linked list, also know as Chunk - Linked list element*, also know as Burst *CB*, also know as Change Bit,it's a control bit (and typically is toggled) that allows to easilyidentify and differentiate between the current linked list and theprevious or the next one. - LLP, is a special element that indicates the end of the linked listelement stream also informs that the next CB should be toggleOn every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 oreven Burst #129) is set some flags on their control variable (RIE andLIE bits) that will trigger the send of "done" interruption.On the interruptions callback, is decided whether to recycle the linkedlist memory space by writing a new set of Bursts elements (if stillexists Chunks to transfer) or is considered completed (if there is noChunks available to transfer).On scatter-gather transfer mode, the client will submit a scatter-gatherlist of n (on this case 130) elements, that will be divide in multipleChunks, each Chunk will have (on this case 42) a limited number ofBursts and after transferring all Bursts, an interrupt will betriggered, which will allow to recycle the all linked list dedicatedmemory again with the new information relative to the next Chunk andrespective Burst associated and repeat the whole cycle again.On cyclic transfer mode, the client will submit a buffer pointer, lengthof it and number of repetitions, in this case each burst will corresponddirectly to each repetition.Each Burst can describes a data transfer from point A(source) to pointB(destination) with a length that can be from 1 byte up to 4 GB. Sincededicated the memory space where the linked list will reside is limited,the whole n burst elements will be organized in several Chunks, thatwill be used later to recycle the dedicated memory space to initiate anew sequence of data transfers.The whole transfer is considered has completed when it was transferredall bursts.Currently this IP has a set well-known register map, which includessupport for legacy and unroll modes. Legacy mode is version of thisregister map that has multiplexer register that allows to switchregisters between all write and read channels and the unroll modesrepeats all write and read channels registers with an offset betweenthem. This register map is called v0.The IP team is creating a new register map more suitable to the latestPCIe features, that very likely will change the map register, which thisversion will be called v1. As soon as this new version is released bythe IP team the support for this version in be included on this driver.According to the logic, patches 1, 2 and 3 should be squashed into 1unique patch, but for the sake of simplicity of review, it was dividedin this 3 patches files.Signed-off-by: Gustavo Pimentel Cc: Vinod Koul Cc: Dan Williams Cc: Andy Shevchenko Cc: Russell King Cc: Joao Pinto Signed-off-by: Vinod Koul List of files: /linux-6.15/drivers/dma/dw-edma/Makefile