Changes in Makefile

36f257e3 - acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors

Mon, 10 Mar 2025 22:38:38 +0000

acpi/ghes, cxl/pci: Process CXL CPER Protocol ErrorsWhen PCIe AER is in FW-First, OS should process CXL Protocol errors fromCPER records. Introduce support for handling and logging CXL Protocolerrors.The defined trace events cxl_aer_uncorrectable_error andcxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse themto trace FW-First Protocol errors.Since the CXL code is required to be called from process context andGHES is in interrupt context, use workqueues for processing.Similar to CXL CPER event handling, use kfifo to handle errors as itsimplifies queue processing by providing lock free fifo operations.Add the ability for the CXL sub-system to register a workqueue toprocess CXL CPER protocol errors.[DJ: return cxl_cper_register_prot_err_work() directly in cxl_ras_init()]Signed-off-by: Smita Koralahalli Reviewed-by: Li Ming Reviewed-by: Alison Schofield Reviewed-by: Ira Weiny Reviewed-by: Tony Luck Link: https://patch.msgid.link/20250310223839.31342-2-Smita.KoralahalliChannabasappa@amd.comSigned-off-by: Dave Jiang List of files: /linux-6.15/drivers/cxl/core/Makefile

516e5bd0 - cxl: Add mce notifier to emit aliased address for extended linear cache

Wed, 26 Feb 2025 16:21:21 +0000

cxl: Add mce notifier to emit aliased address for extended linear cacheBelow is a setup with extended linear cache configuration with an examplelayout of memory region shown below presented as a single memory regionconsists of 256G memory where there's 128G of DRAM and 128G of CXL memory.The kernel sees a region of total 256G of system memory. 128G DRAM 128G CXL memory|-----------------------------------|-------------------------------------|Data resides in either DRAM or far memory (FM) with no replication. Hotdata is swapped into DRAM by the hardware behind the scenes. When error isdetected in one location, it is possible that error also resides in thealiased location. Therefore when a memory location that is flagged by MCEis part of the special region, the aliased memory location needs to beofflined as well.Add an mce notify callback to identify if the MCE address location is partof an extended linear cache region and handle accordingly.Added symbol export to set_mce_nospec() in x86 code in order to callset_mce_nospec() from the CXL MCE notify callback.Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20250226162224.3633792-5-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/drivers/cxl/core/Makefile

0ec9849b - acpi/hmat / cxl: Add extended linear cache support for CXL

Wed, 26 Feb 2025 16:21:19 +0000

acpi/hmat / cxl: Add extended linear cache support for CXLThe current cxl region size only indicates the size of the CXL memoryregion without accounting for the extended linear cache size. Retrieve thecache size from HMAT and append that to the cxl region size for the cxlregion range that matches the SRAT range that has extended linear cacheenabled.The SRAT defines the whole memory range that includes the extended linearcache and the CXL memory region. The new HMAT ECN/ECR to the Memory SideCache Information Structure defines the size of the extended linear cachesize and matches to the SRAT Memory Affinity Structure by the memoryproxmity domain. Add a helper to match the cxl range to the SRAT memoryrange in order to retrieve the cache size.There are several places that checks the cxl region range against thedecoder range. Use new helper to check between the two ranges and addressthe new cache size.Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20250226162224.3633792-3-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/drivers/cxl/core/Makefile

f0e6a232 - cxl: Add Get Supported Features command for kernel usage

Thu, 20 Feb 2025 19:42:40 +0000

cxl: Add Get Supported Features command for kernel usageCXL spec r3.2 8.2.9.6.1 Get Supported Features (Opcode 0500h)The command retrieve the list of supported device-specific features(identified by UUID) and general information about each Feature.The driver will retrieve the Feature entries in order to make checks andprovide information for the Get Feature and Set Feature command. One ofthe main piece of information retrieved are the effects a Set Featurecommand would have for a particular feature. The retrieved Featureentries are stored in the cxl_mailbox context.The setup of Features is initiated via devm_cxl_setup_features() during thepci probe function before the cxl_memdev is enumerated.Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Reviewed-by: Li Ming Reviewed-by: Davidlohr Bueso Tested-by: Shiju Jose Link: https://patch.msgid.link/20250220194438.2281088-3-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux-6.15/drivers/cxl/core/Makefile

ad6f04c0 - cxl: Add callback to parse the DSMAS subtables from CDAT

Thu, 21 Dec 2023 22:03:13 +0000

cxl: Add callback to parse the DSMAS subtables from CDATProvide a callback function to the CDAT parser in order to parse theDevice Scoped Memory Affinity Structure (DSMAS). Each DSMAS structurecontains the DPA range and its associated attributes in each entry. Seethe CDAT specification for details. The device handle and the DPA rangeis saved and to be associated with the DSLBIS locality data when theDSLBIS entries are parsed. The xarray is a local variable. When thetotal path performance data is calculated and storred this xarray can bediscarded.Coherent Device Attribute Table 1.03 2.1 Device Scoped memory AffinityStructure (DSMAS)Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/170319619355.2212653.2675953129671561293.stgit@djiang5-mobl3Signed-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

1ad3f701 - cxl/pci: Find and register CXL PMU devices

Fri, 26 May 2023 09:58:22 +0000

cxl/pci: Find and register CXL PMU devicesCXL PMU devices can be found from entries in the RegisterLocator DVSEC.Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230526095824.16336-4-Jonathan.Cameron@huawei.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

4a20bc3e - cxl/pci: Move tracepoint definitions to drivers/cxl/core/

Thu, 08 Dec 2022 17:02:00 +0000

cxl/pci: Move tracepoint definitions to drivers/cxl/core/CXL is using tracepoints for reporting RAS capability register payloadsfor AER events, and has plans to use tracepoints for the output payloadof Get Poison List and Get Event Records commands. For organizationpurposes it would be nice to keep those all under a single + local CXLtrace system. This also organization also potentially helps in thefuture when CXL drivers expand beyond generic memory expanders, howeverthat would also entail a move away from the expander-specificcxl_dev_state context, save that for later.Note that the powerpc-specific drivers/misc/cxl/ also defines a 'cxl'trace system, however, it is unlikely that a single platform will everload both drivers simultaneously.Cc: Steven Rostedt Tested-by: Alison Schofield Reviewed-by: Dave Jiang Link: https://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

779dd20c - cxl/region: Add region creation support

Tue, 08 Jun 2021 17:28:34 +0000

cxl/region: Add region creation supportCXL 2.0 allows for dynamic provisioning of new memory regions (systemphysical address resources like "System RAM" and "Persistent Memory").Whereas DDR and PMEM resources are conveyed statically at boot, CXLallows for assembling and instantiating new regions from the availablecapacity of CXL memory expanders in the system.Sysfs with an "echo $region_name > $create_region_attribute" interfaceis chosen as the mechanism to initiate the provisioning process. Thiswas chosen over ioctl() and netlink() to keep the configurationinterface entirely in a pseudo-fs interface, and it was chosen overconfigfs since, aside from this one creation event, the interface isread-mostly. I.e. configfs supports cases where an object is designed tobe provisioned each boot, like an iSCSI storage target, and CXL regioncreation is mostly for PMEM regions which are created usually onceper-lifetime of a server instance. This is an improvement over nvdimmthat pre-created "seed" devices that tended to confuse users looking todetermine which devices are active and which are idle.Recall that the major change that CXL brings over previous persistentmemory architectures is the ability to dynamically define new regions.Compare that to drivers like 'nfit' where the region configuration isstatically defined by platform firmware.Regions are created as a child of a root decoder that encompasses anaddress space with constraints. When created through sysfs, the rootdecoder is explicit. When created from an LSA's region structure a rootdecoder will possibly need to be inferred by the driver.Upon region creation through sysfs, a vacant region is created with aunique name. Regions have a number of attributes that must be configuredbefore the region can be bound to the driver where HDM decoder programis completed.An example of creating a new region:- Allocate a new region name:region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)- Create a new region by name:whileregion=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_regiondo true; done- Region now exists in sysfs:stat -t /sys/bus/cxl/devices/decoder0.0/$region- Delete the region, and name:echo $region > /sys/bus/cxl/devices/decoder0.0/delete_regionSigned-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com[djbw: simplify locking, reword changelog]Signed-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

9ea4dcf4 - PM: CXL: Disable suspend

Fri, 22 Apr 2022 22:58:11 +0000

PM: CXL: Disable suspendThe CXL specification claims S3 support at a hardware level, but at asystem software level there are some missing pieces. Section 9.4 (CXL2.0) rightly claims that "CXL mem adapters may need aux power to retainmemory context across S3", but there is no enumeration mechanism for theOS to determine if a given adapter has that support. Moreover the savestate and resume image for the system may inadvertantly end up in a CXLdevice that needs to be restored before the save state is recoverable.I.e. a circular dependency that is not resolvable without a third partysave-area.Arrange for the cxl_mem driver to fail S3 attempts. This still nominalyallows for suspend, but requires unbinding all CXL memory devices beforethe suspend to ensure the typical DRAM flow is taken. The cxl_mem unbindflow is intended to also tear down all CXL memory regions associatedwith a given cxl_memdev.It is reasonable to assume that any device participating in a System RAMrange published in the EFI memory map is covered by aux power andsave-area outside the device itself. So this restriction can beminimized in the future once pre-existing region enumeration supportarrives, and perhaps a spec update to clarify if the EFI memory map issufficent for determining the range of devices managed byplatform-firmware for S3 support.Per Rafael, if the CXL configuration prevents suspend then it shouldfail early before tasks are frozen, and mem_sleep should stop showing'mem' as an option [1]. Effectively CXL augments the platform suspend->valid() op since, for example, the ACPI ops are not aware of the CXL /PCI dependencies. Given the split role of platform firmware vs OSprovisioned CXL memory it is up to the cxl_mem driver to determine ifthe CXL configuration has elements that platform firmware may not beprepared to restore.Link: https://lore.kernel.org/r/CAJZ5v0hGVN_=3iU8OLpHY3Ak35T5+JcBM-qs8SbojKrpd0VXsA@mail.gmail.com [1]Cc: "Rafael J. Wysocki" Cc: Pavel Machek Cc: Len Brown Reviewed-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/165066828317.3907920.5690432272182042556.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

d17d0540 - cxl/core/hdm: Add CXL standard decoder enumeration to the core

Tue, 01 Feb 2022 20:24:30 +0000

cxl/core/hdm: Add CXL standard decoder enumeration to the coreUnlike the decoder enumeration for "root decoders" described by platformfirmware, standard decoders can be enumerated from the componentregisters space once the base address has been identified (via PCI,ACPI, or another mechanism).Add common infrastructure for HDM (Host-managed-Device-Memory) Decoderenumeration and share it between host-bridge, upstream switch port, andcxl_test defined decoders.The locking model for switch level decoders is to hold the port lockover the enumeration. This facilitates moving the dport and decoderenumeration to a 'port' driver. For now, the only enumerator of decoderresources is the cxl_acpi root driver.Co-developed-by: Ben Widawsky Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/164374688404.395335.9239248252443123526.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

98d2d3a2 - cxl/core: Generalize dport enumeration in the core

Tue, 01 Feb 2022 02:10:04 +0000

cxl/core: Generalize dport enumeration in the coreThe core houses infrastructure for decoder resources. A CXL port'sdports are more closely related to decoder infrastructure than topologyenumeration. Implement generic PCI based dport enumeration in the core,i.e. arrange for existing root port enumeration from cxl_acpi to sharecode with switch port enumeration which just amounts to a smalldifference in a pci_walk_bus() invocation once the appropriate 'structpci_bus' has been retrieved.Set the convention that decoder objects are registered after all dportsare enumerated. This enables userspace to know when the CXL core isfinished establishing 'dportX' links underneath the 'portX' object.Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/164368114191.354031.5270501846455462665.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

0ff0af18 - cxl/core/port: Rename bus.c to port.c

Mon, 24 Jan 2022 00:29:21 +0000

cxl/core/port: Rename bus.c to port.cGiven it is dominated by port infrastructure, and will only acquiremore, rename bus.c to port.c.Reviewed-by: Ben Widawsky Link: https://lore.kernel.org/r/164298416136.3018233.15442880970000855425.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

affec782 - cxl/core: Convert to EXPORT_SYMBOL_NS_GPL

Sat, 13 Nov 2021 00:32:58 +0000

cxl/core: Convert to EXPORT_SYMBOL_NS_GPLIt turns out that the usb example of specifying the subsystem namespaceat build time is not preferred. The rationale for that preference hasbecome more apparent as CXL patches with plain EXPORT_SYMBOL_GPL beg thequestion, "why would any code other than CXL care about this symbol?".Make the namespace explicit.Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/163676356810.3618264.601632777702192938.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

4faf31b4 - cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the core

Thu, 09 Sep 2021 05:12:32 +0000

cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreNow that the internals of mailbox operations are abstracted from the PCIspecifics a bulk of infrastructure can move to the core.The CXL_PMEM driver intends to proxy LIBNVDIMM UAPI and driver requeststo the equivalent functionality provided by the CXL hardware mailboxinterface. In support of that intent move the mailbox implementation toa shared location for the CXL_PCI driver native IOCTL path and CXL_PMEMnvdimm command proxy path to share.A unit test framework seeks to implement a unit test backend transportfor mailbox commands to communicate mocked up payloads. It can reuse allof the mailbox infrastructure minus the PCI specifics, so that also getsmoved to the core.Finally with the mailbox infrastructure and ioctl handling beingtransport generic there is no longer any need to pass filefile_operations to devm_cxl_add_memdev(). That allows all the ioctlboilerplate to move into the core for unit test reuse.No functional change intended, just code movement.Acked-by: Ben Widawsky Reported-by: kernel test robot Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/163116435233.2460985.16197340449713287180.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

3d135db5 - cxl/core: Move memdev management to core

Mon, 02 Aug 2021 17:30:05 +0000

cxl/core: Move memdev management to coreThe motivation for moving cxl_memdev allocation to the core (beyondbetter file organization of sysfs attributes in core/ and drivers incxl/), is that device lifetime is longer than module lifetime. The cxl_pcimodule should be free to come and go without needing to coordinate withdevices that need the text associated with cxl_memdev_release() to stayresident. The move fixes a use after free bug when looping driverload / unload with CONFIG_DEBUG_KOBJECT_RELEASE=y.Another motivation for disconnecting cxl_memdev creation from cxl_pci isto enable other drivers, like a unit test driver, to registers memdevs.Fixes: b39cb1052a5c ("cxl/mem: Register CXL memX devices")Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162792540495.368511.9748638751088219595.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

0f06157e - cxl/core: Move register mapping infrastructure

Tue, 03 Aug 2021 14:25:38 +0000

cxl/core: Move register mapping infrastructureThe register mapping infrastructure is large enough to move to its owncompilation unit. This also cleans up an unnecessary include of core/bus.c.Reported-by: kernel test robot Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162800068975.665205.12895551621746585289.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

06737cd0 - cxl/core: Move pmem functionality

Mon, 02 Aug 2021 17:29:49 +0000

cxl/core: Move pmem functionalityRefactor the pmem / nvdimm-bridge functionality from core/bus.c tocore/pmem.c. Introduce drivers/core/core.h to communicate datastructures and helpers between the core bus and other functionality thatregisters devices on the bus.Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162792538899.368511.3881663908293411300.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile

5161a55c - cxl: Move cxl_core to new directory

Mon, 02 Aug 2021 17:29:38 +0000

cxl: Move cxl_core to new directoryCXL core is growing, and it's already arguably unmanageable. To supportfuture growth, move core functionality to a new directory and rename thefile to represent just bus support. Future work will remove non-busfunctionality.Note that mem.h is renamed to cxlmem.h to avoid a namespace collisionwith the global ARCH=um mem.h header.Reported-by: kernel test robot Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162792537866.368511.8915631504621088321.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/core/Makefile