Changes in Makefile

6575b268 - cxl/port: Fix CXL port initialization order when the subsystem is built-in

Fri, 25 Oct 2024 19:32:55 +0000

cxl/port: Fix CXL port initialization order when the subsystem is built-inWhen the CXL subsystem is built-in the module init order is determinedby Makefile order. That order violates expectations. The expectation isthat cxl_acpi and cxl_mem can race to attach. If cxl_acpi wins the race,cxl_mem will find the enabled CXL root ports it needs. If cxl_acpi losesthe race it will retrigger cxl_mem to attach via cxl_bus_rescan(). Thatflow only works if cxl_acpi can assume ports are enabled immediatelyupon cxl_acpi_probe() return. That in turn can only happen in theCONFIG_CXL_ACPI=y case if the cxl_port driver is registered beforecxl_acpi_probe() runs.Fix up the order to prevent initialization failures. Ensure thatcxl_port is built-in when cxl_acpi is also built-in, arrange forMakefile order to resolve the subsys_initcall() order of cxl_port andcxl_acpi, and arrange for Makefile order to resolve thedevice_initcall() (module_init()) order of the remaining objects.As for what contributed to this not being found earlier, the CXLregression environment, cxl_test, builds all CXL functionality as amodule to allow to symbol mocking and other dynamic reload tests. As aresult there is no regression coverage for the built-in case.Reported-by: Gregory Price Closes: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.netTested-by: Gregory Price Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver")Cc: stable@vger.kernel.orgCc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Reviewed-by: Jonathan Cameron Reviewed-by: Ira Weiny Tested-by: Alejandro Lucero Reviewed-by: Alejandro Lucero Signed-off-by: Dan Williams Link: https://patch.msgid.link/172988474904.476062.7961350937442459266.stgit@dwillia2-xfh.jf.intel.comSigned-off-by: Ira Weiny List of files: /linux-6.15/drivers/cxl/Makefile

32828115 - cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation

Wed, 30 Nov 2022 19:21:36 +0000

cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationAdd nvdimm_security_ops support for CXL memory device with the introductionof the ->get_flags() callback function. This is part of the "PersistentMemory Data-at-rest Security" command set for CXL memory device support.The ->get_flags() function provides the security state of the persistentmemory device defined by the CXL 3.0 spec section 8.2.9.8.6.1.Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Link: https://lore.kernel.org/r/166983609611.2734609.13231854299523325319.stgit@djiang5-desk3.ch.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

9ea4dcf4 - PM: CXL: Disable suspend

Fri, 22 Apr 2022 22:58:11 +0000

PM: CXL: Disable suspendThe CXL specification claims S3 support at a hardware level, but at asystem software level there are some missing pieces. Section 9.4 (CXL2.0) rightly claims that "CXL mem adapters may need aux power to retainmemory context across S3", but there is no enumeration mechanism for theOS to determine if a given adapter has that support. Moreover the savestate and resume image for the system may inadvertantly end up in a CXLdevice that needs to be restored before the save state is recoverable.I.e. a circular dependency that is not resolvable without a third partysave-area.Arrange for the cxl_mem driver to fail S3 attempts. This still nominalyallows for suspend, but requires unbinding all CXL memory devices beforethe suspend to ensure the typical DRAM flow is taken. The cxl_mem unbindflow is intended to also tear down all CXL memory regions associatedwith a given cxl_memdev.It is reasonable to assume that any device participating in a System RAMrange published in the EFI memory map is covered by aux power andsave-area outside the device itself. So this restriction can beminimized in the future once pre-existing region enumeration supportarrives, and perhaps a spec update to clarify if the EFI memory map issufficent for determining the range of devices managed byplatform-firmware for S3 support.Per Rafael, if the CXL configuration prevents suspend then it shouldfail early before tasks are frozen, and mem_sleep should stop showing'mem' as an option [1]. Effectively CXL augments the platform suspend->valid() op since, for example, the ACPI ops are not aware of the CXL /PCI dependencies. Given the split role of platform firmware vs OSprovisioned CXL memory it is up to the cxl_mem driver to determine ifthe CXL configuration has elements that platform firmware may not beprepared to restore.Link: https://lore.kernel.org/r/CAJZ5v0hGVN_=3iU8OLpHY3Ak35T5+JcBM-qs8SbojKrpd0VXsA@mail.gmail.com [1]Cc: "Rafael J. Wysocki" Cc: Pavel Machek Cc: Len Brown Reviewed-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/165066828317.3907920.5690432272182042556.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

8dd2bc0f - cxl/mem: Add the cxl_mem driver

Fri, 04 Feb 2022 15:18:31 +0000

cxl/mem: Add the cxl_mem driverAt this point the subsystem can enumerate all CXL ports (CXL.mem decoderesources in upstream switch ports and host bridges) in a system. Thelast mile is connecting those ports to endpoints.The cxl_mem driver connects an endpoint device to the platform CXL.memprotoctol decode-topology. At ->probe() time it walks itsdevice-topology-ancestry and adds a CXL Port object at every UpstreamPort hop until it gets to CXL root. The CXL root object is only presentafter a platform firmware driver registers platform CXL resources. ForACPI based platform this is managed by the ACPI0017 device and thecxl_acpi driver.The ports are registered such that disabling a given port automaticallyunregisters all descendant ports, and the chain can only be registeredafter the root is established.Given ACPI device scanning may run asynchronously compared to PCI devicescanning the root driver is tasked with rescanning the bus after theroot successfully probes.Conversely if any ports in a chain between the root and an endpointbecomes disconnected it subsequently triggers the endpoint tounregister. Given lock depenedencies the endpoint unregistration happensin a workqueue asynchronously. If userspace cares about synchronizingdelayed work after port events the /sys/bus/cxl/flush attribute isavailable for that purpose.Reported-by: Randy Dunlap Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron [djbw: clarify changelog, rework hotplug support]Link: https://lore.kernel.org/r/164398782997.903003.9725273241627693186.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

54cdbf84 - cxl/port: Add a driver for 'struct cxl_port' objects

Tue, 01 Feb 2022 21:07:51 +0000

cxl/port: Add a driver for 'struct cxl_port' objectsThe need for a CXL port driver and a dedicated cxl_bus_type is driven bya need to simultaneously support 2 independent physical memory decodedomains (cache coherent CXL.mem and uncached PCI.mmio) that alsointersect at a single PCIe device node. A CXL Port is a device thatadvertises a CXL Component Register block with an "HDM DecoderCapability Structure".>From Documentation/driver-api/cxl/memory-devices.rst: Similar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.The port driver identifies whether an endpoint Memory Expander isconnected to a CXL topology. If an active (bound to the 'cxl_port'driver) CXL Port is not found at every PCIe Switch Upstream port and anactive "root" CXL Port then the device is just a plain PCIe endpointonly capable of participating in PCI.mmio and DMA cycles, not CXL.memcoherent interleave sets.The 'cxl_port' driver lets the CXL subsystem leverage driver-coreinfrastructure for setup and teardown of register resources andcommunicating device activation status to userspace. The cxl_bus_typecan rendezvous the async arrival of platform level CXL resources (viathe 'cxl_acpi' driver) with the asynchronous enumeration of MemoryExpander endpoints, while also implementing a hierarchical locking modelindependent of the associated 'struct pci_dev' locking model. Thelocking for dport and decoder enumeration is now handled in the corerather than callers.For now the port driver only enumerates and registers CXL resources(downstream port metadata and decoder resources) later it will be usedto take action on its decoders in response to CXL.mem regionprovisioning requests.Note1: cxlpci.h has long depended on pci.h, but port.c was the first tonot include pci.h. Carry that dependency in cxlpci.h.Note2: cxl port enumeration and probing complicates CXL subsystem initto the point that it helps to have centralized debug logging of probeevents in cxl_bus_probe().Reported-by: kernel test robot Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Co-developed-by: Dan Williams Link: https://lore.kernel.org/r/164374948116.464348.1772618057599155408.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

68cdd3d2 - cxl: Rename CXL_MEM to CXL_PCI

Mon, 24 Jan 2022 00:28:44 +0000

cxl: Rename CXL_MEM to CXL_PCIThe cxl_mem module was renamed cxl_pci in commit 21e9f76733a8 ("cxl:Rename mem to pci"). In preparation for adding an ancillary driver forcxl_memdev devices (registered on the cxl bus by cxl_pci), go ahead andrename CONFIG_CXL_MEM to CONFIG_CXL_PCI. Free up the CXL_MEM name forthat new driver to manage CXL.mem endpoint operations.Suggested-by: Dan Williams Reviewed-by: Jonathan Cameron Signed-off-by: Ben Widawsky Link: https://lore.kernel.org/r/164298412409.3018233.12407355692407890752.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

5161a55c - cxl: Move cxl_core to new directory

Mon, 02 Aug 2021 17:29:38 +0000

cxl: Move cxl_core to new directoryCXL core is growing, and it's already arguably unmanageable. To supportfuture growth, move core functionality to a new directory and rename thefile to represent just bus support. Future work will remove non-busfunctionality.Note that mem.h is renamed to cxlmem.h to avoid a namespace collisionwith the global ARCH=um mem.h header.Reported-by: kernel test robot Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162792537866.368511.8915631504621088321.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

8fdcb170 - cxl/pmem: Add initial infrastructure for pmem support

Tue, 15 Jun 2021 23:18:17 +0000

cxl/pmem: Add initial infrastructure for pmem supportRegister an 'nvdimm-bridge' device to act as an anchor for a libnvdimmbus hierarchy. Also, flesh out the cxl_bus definition to allow acxl_nvdimm_bridge_driver to attach to the bridge and trigger thenvdimm-bus registration.The creation of the bridge is gated on the detection of a PMEM capableaddress space registered to the root. The bridge indirection allows thelibnvdimm module to remain unloaded on platforms without PMEM support.Given that the probing of ACPI0017 is asynchronous to CXL endpointdevices, and the expectation that CXL endpoint devices register otherPMEM resources on the 'CXL' nvdimm bus, a workqueue is added. Theworkqueue is needed to run bus_rescan_devices() outside of thedevice_lock() of the nvdimm-bridge device to rendezvous nvdimm resourcesas they arrive. For now only the bus is taken online/offline in theworkqueue.Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162379909706.2993820.14051258608641140169.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

4812be97 - cxl/acpi: Introduce the root of a cxl_port topology

Wed, 09 Jun 2021 16:01:35 +0000

cxl/acpi: Introduce the root of a cxl_port topologyWhile CXL builds upon the PCI software model for enumeration andendpoint control, a static platform component is required to bootstrapthe CXL memory layout. Similar to how ACPI identifies root-level PCImemory resources, ACPI data enumerates the address space and interleaveconfiguration for CXL Memory.In addition to identifying host bridges, ACPI is responsible forenumerating the CXL memory space that can be addressed by downstreamdecoders. This is similar to the requirement for ACPI to publishresources via the _CRS method for PCI host bridges. Specifically, ACPIpublishes a table, CXL Early Discovery Table (CEDT), which includes alist of CXL Memory resources, CXL Fixed Memory Window Structures(CFMWS).For now, introduce the core infrastructure for a cxl_port hierarchystarting with a root level anchor represented by the ACPI0017 device.Follow on changes model support for the configurable decode capabilitiesof cxl_port instances, i.e. CXL switch support.Co-developed-by: Alison Schofield Signed-off-by: Alison Schofield Acked-by: Rafael J. Wysocki Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162325449515.2293126.15303270193010154608.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

21e9f767 - cxl: Rename mem to pci

Wed, 26 May 2021 17:44:13 +0000

cxl: Rename mem to pciAs the driver has undergone development, it's become clear that themajority [entirety?] of the current functionality in mem.c is actually alayer encapsulating functionality exposed through PCI basedinteractions. This layer can be used either in isolation or to providefunctionality for higher level functionality.CXL capabilities exist in a parallel domain to PCIe. CXL devices areenumerable and controllable via "legacy" PCIe mechanisms; however, theirCXL capabilities are a superset of PCIe. For example, a CXL device maybe connected to a non-CXL capable PCIe root port, and therefore will notbe able to participate in CXL.mem or CXL.cache operations, but can stillbe accessed through PCIe mechanisms for CXL.io operations.To properly represent the PCI nature of this driver, and in preparation forintroducing a new driver for the CXL.mem / HDM decoder (Host-managed DeviceMemory) capabilities of a CXL memory expander, rename mem.c to pci.c so thatmem.c is available for this new driver.The result of the change is that there is a clear layering distinctionin the driver, and a systems administrator may load only the cxl_pcimodule and gain access to such operations as, firmware update, offlineprovisioning of devices, and error collection. In addition to freeing upthe file name for another purpose, there are two primary reasons this isuseful, 1. Acting upon devices which don't have full CXL capabilities. This may happen for instance if the CXL device is connected in a CXL unaware part of the platform topology. 2. Userspace-first provisioning for devices without kernel driver interference. This may be useful when provisioning a new device in a specific manner that might otherwise be blocked or prevented by the real CXL mem driver.Reviewed-by: Dan Williams Signed-off-by: Ben Widawsky Link: https://lore.kernel.org/r/20210526174413.802913-1-ben.widawsky@intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

5f653f75 - cxl/core: Rename bus.c to core.c

Fri, 14 May 2021 05:22:00 +0000

cxl/core: Rename bus.c to core.cIn preparation for more generic shared functionality across endpointconsumers of core cxl resources, and platform-firmware producers ofthose resources, rename bus.c to core.c. In addition to the centralrendezvous for interleave coordination, the core will also define commonroutines like CXL register block mapping.Acked-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/162096972018.1865304.11079951161445408423.stgit@dwillia2-desk3.amr.corp.intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

b39cb105 - cxl/mem: Register CXL memX devices

Wed, 17 Feb 2021 04:09:52 +0000

cxl/mem: Register CXL memX devicesCreate the /sys/bus/cxl hierarchy to enumerate:* Memory Devices (per-endpoint control devices)* Memory Address Space Devices (platform address ranges with interleaving, performance, and persistence attributes)* Memory Regions (active provisioned memory from an address space device that is in use as System RAM or delegated to libnvdimm as Persistent Memory regions).For now, only the per-endpoint control devices are registered on the'cxl' bus. However, going forward it will provide a mechanism tocoordinate cross-device interleave.Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron (v2)Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile

4cdadfd5 - cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints

Wed, 17 Feb 2021 04:09:50 +0000

cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpointsThe CXL.mem protocol allows a device to act as a provider of "SystemRAM" and/or "Persistent Memory" that is fully coherent as if the memorywas attached to the typical CPU memory controller.With the CXL-2.0 specification a PCI endpoint can implement a "Type-3"device interface and give the operating system control over "HostManaged Device Memory". See section 2.3 Type 3 CXL Device.The memory range exported by the device may optionally be described bythe platform firmware memory map, or by infrastructure like LIBNVDIMM toprovision persistent memory capacity from one, or more, CXL.mem devices.A pre-requisite for Linux-managed memory-capacity provisioning is thiscxl_mem driver that can speak the mailbox protocol defined in section8.2.8.4 Mailbox Registers.For now just land the initial driver boiler-plate and Documentation/infrastructure.Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Acked-by: David Rientjes (v1)Cc: Jonathan Corbet Link: https://www.computeexpresslink.org/download-the-specificationLink: https://lore.kernel.org/r/20210217040958.1354670-2-ben.widawsky@intel.comSigned-off-by: Dan Williams List of files: /linux-6.15/drivers/cxl/Makefile