Changes in Makefile

b1bc04a2 - clk: tegra: Support runtime PM and power domain

Tue, 30 Nov 2021 23:23:12 +0000

clk: tegra: Support runtime PM and power domainThe Clock-and-Reset controller resides in a core power domain on NVIDIATegra SoCs. In order to support voltage scaling of the core power domain,we hook up DVFS-capable clocks to the core GENPD for managing of theGENPD's performance state based on the clock changes.Some clocks don't have any specific physical hardware unit that backsthem, like root PLLs and system clock and they have theirs own voltagerequirements. This patch adds new clk-device driver that backs the clocksand provides runtime PM functionality for them. A virtual clk-device iscreated for each such DVFS-capable clock at the clock's registration timeby the new tegra_clk_register() helper. Driver changes clock's deviceGENPD performance state based on clk-rate notifications.In result we have this sequence of events: 1. Clock driver creates virtual device for selective clocks, enables runtime PM for the created device and registers the clock. 2. Clk-device driver starts to listen to clock rate changes. 3. Something changes clk rate or enables/disables clk. 4. CCF core propagates the change through the clk tree. 5. Clk-device driver gets clock rate-change notification or GENPD core handles prepare/unprepare of the clock. 6. Clk-device driver changes GENPD performance state on clock rate change. 7. GENPD driver changes voltage regulator state change. 8. The regulator state is committed to hardware via I2C.We rely on fact that DVFS is not needed for Tegra I2C and that Tegra I2Cdriver already keeps clock always-prepared. Hence I2C subsystem staysindependent from the clk power management and there are no deadlock spotsin the sequence.Currently all clocks are registered very early during kernel boot when thedevice driver core isn't available yet. The clk-device can't be createdat that time. This patch splits the registration of the clocks in twophases: 1. Register all essential clocks which don't use RPM and are needed during early boot. 2. Register at a later boot time the rest of clocks.This patch adds power management support for Tegra20 and Tegra30 clocks.Reviewed-by: Ulf Hansson Tested-by: Peter Geis # Ouya T30Tested-by: Paul Fertser # PAZ00 T20Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124Tested-by: Matt Merhar # Ouya T30Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

281462e5 - memory: tegra124-emc: Make driver modular

Mon, 28 Dec 2020 15:49:16 +0000

memory: tegra124-emc: Make driver modularAdd modularization support to the Tegra124 EMC driver, which now can becompiled as a loadable kernel module.Note that EMC clock must be registered at clk-init time, otherwise PLLMwill be disabled as unused clock at boot time if EMC driver is compiledas a module. Hence add a prepare/complete callbacks. similarly to what isdone for the Tegra20/30 EMC drivers.Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.comSigned-off-by: Krzysztof Kozlowski List of files: /linux-6.15/drivers/clk/tegra/Makefile

16415679 - clk: tegra: Add custom CCLK implementation

Thu, 19 Mar 2020 19:02:18 +0000

clk: tegra: Add custom CCLK implementationCCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supportsmultiple parents, it has internal clock divider and a clock skipper.PLLX is the main CCLK parent that provides clock rates above 1GHz and ithas special property such that the CCLK's internal divider is set intobypass mode when PLLX is selected as a parent for CCLK.This patch forks generic Super Clock into CCLK implementation which takesinto account all CCLK specifics. The proper CCLK implementation is neededby the upcoming Tegra20 CPUFreq driver update that will allow to utilizethe generic cpufreq-dt driver by moving intermediate clock selection intothe clock driver.Note that technically this patch could be squashed into clk-super.c, butit is cleaner to have a separate source file. Also note that currently allCCLKLP bits are left in the clk-super.c and only CCLKG is supported byclk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits,but CCLKLP is not used by anything in kernel and thus better not to touchit for now.Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

0ac65fc9 - clk: tegra: Implement Tegra210 EMC clock

Wed, 29 May 2019 08:21:35 +0000

clk: tegra: Implement Tegra210 EMC clockThe EMC clock needs to carefully coordinate with the EMC controllerprogramming to make sure external memory can be properly clocked. Do soby hooking up the EMC clock with an EMC provider that will specify whichrates are supported by the EMC and provide a callback to use for settingthe clock rate at the EMC.Based on work by Peter De Schrijver .Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

3dcbd36f - clk: tegra: Rename Tegra124 EMC clock source file

Fri, 28 Feb 2020 11:43:51 +0000

clk: tegra: Rename Tegra124 EMC clock source fileThis code is only used on Tegra124, so rename it accordingly to make itmore consistent with other file names.While at it, also get rid of the TEGRA_CLK_EMC Kconfig symbol that'sreally just an alias for TEGRA124_EMC.Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

acbeec3d - clk: tegra: Remove tegra_pmc_clk_init along with clk ids

Tue, 14 Jan 2020 07:24:25 +0000

clk: tegra: Remove tegra_pmc_clk_init along with clk idsCurrent Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,clk_out_3 and 32KHz blink output in tegra_pmc_init() which does directPMC register access during clk_ops and these PMC register read and writeaccess will not happen when PMC is in secure mode.Any direct PMC register access from non-secure world will not gothrough.All the PMC clocks are moved to Tegra PMC driver with PMC as a clockprovider.This patch removes tegra_pmc_clk_init along with corresponding clk idsfrom Tegra clock driver.Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

ed1a2459 - clk: tegra: Add Tegra20/30 EMC clock implementation

Sun, 11 Aug 2019 21:00:29 +0000

clk: tegra: Add Tegra20/30 EMC clock implementationA proper External Memory Controller clock rounding and parent selectionfunctionality is required by the EMC drivers, it is not available usingthe generic clock implementation because only the Memory Controller driveris aware of what clock rates are actually available for a particulardevice. EMC drivers will have to register a Tegra-specific CLK-APIcallback which will perform rounding of a requested rate. EMC clock userswon't be able to request EMC clock by getting -EPROBE_DEFER until EMCdriver is probed and the callback is set up.The functionality is somewhat similar to the clk-emc.c which servesTegra124+ SoCs. The later HW generations support more parent clock sourcesand the HW configuration / integration with the EMC drivers differs a tadfrom the older gens, hence it's not really worth to try to squasheverything into a single source file.Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Acked-by: Stephen Boyd Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

8bf9437a - clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210

Fri, 04 Jan 2019 03:06:52 +0000

clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Tegra210 has a DFLL as well and can share the majority of the code withthe Tegra124 implementation. So build the same code for both platforms.Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Stephen Boyd Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

633e7965 - clk: tegra: Add sdmmc mux divider clock

Thu, 12 Jul 2018 11:53:01 +0000

clk: tegra: Add sdmmc mux divider clockAdd a clock type to model the sdmmc switch divider clocks which have pathsto source clocks bypassing the divider (Low Jitter paths). Theseare handled by selecting the lj path when the divider is 1 (ie therate is the parent rate), otherwise the normal path with dividerwill be selected. Otherwise this clock behaves as a normal peripheralclock.Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver Acked-by: Jon Hunter Signed-off-by: Stephen Boyd List of files: /linux-6.15/drivers/clk/tegra/Makefile

cb3ac594 - clk: tegra: Refactor fractional divider calculation

Thu, 12 Jul 2018 11:53:00 +0000

clk: tegra: Refactor fractional divider calculationMove this to a separate file so it can be used to calculate the sdmmcclock dividers.Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver Acked-by: Jon Hunter Signed-off-by: Stephen Boyd List of files: /linux-6.15/drivers/clk/tegra/Makefile

b2441318 - License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Wed, 01 Nov 2017 14:07:57 +0000

License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseMany source files in the tree are missing licensing information, whichmakes it harder for compliance tools to determine the correct license.By default all files without license information are under the defaultlicense of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'SPDX license identifier. The SPDX identifier is a legally bindingshorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart andPhilippe Ombredanne.How this work was done:Patches were generated and checked against linux-4.14-rc6 for a subset ofthe use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up caseswhere non-standard license headers were used, and references to licensehad to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied toa file was done in a spreadsheet of side by side results from of theoutput of two independent scanners (ScanCode & Windriver) producing SPDXtag:value files created by Philippe Ombredanne. Philippe prepared thebase worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 filesassessed. Kate Stewart did a file by file comparison of the scannerresults in the spreadsheet to determine which SPDX license identifier(s)to be applied to the file. She confirmed any determination that was notimmediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines).All documentation files were explicitly excluded.The following heuristics were used to determine which SPDX licenseidentifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time.In total, over 70 hours of logged manual review was done on thespreadsheet to determine the SPDX license identifiers to apply to thesource files by Kate, Philippe, Thomas and, in some cases, confirmationby lawyers working with the Linux Foundation.Kate also obtained a third independent scan of the 4.13 code base fromFOSSology, and compared selected files where the other two scannersdisagreed against that SPDX file, to see if there was new insights. TheWindriver scanner is based on an older version of FOSSology in part, sothey are related.Thomas did random spot checks in about 500 files from the spreadsheetsfor the uapi headers and agreed with SPDX license identifier in thefiles he inspected. For the non-uapi files Thomas did random spot checksin about 15000 files.In initial set of patches against 4.14-rc6, 3 files were found to havecopy/paste license identifier errors, and have been fixed to reflect thecorrect identifier.Additionally Philippe spent 10 hours this week doing a detailed manualinspection and review of the 12,461 patched files from the initial patchversion early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correctThis produced a worksheet with 20 files needing minor correction. Thisworksheet was then exported into 3 different .csv files for thedifferent types of files to be modified.These .csv files were then reviewed by Greg. Thomas wrote a script toparse the csv files and add the proper SPDX tag to the file, in theformat that the file expected. This script was further refined by Gregbased on the output to detect more types of files automatically and todistinguish between header and source .c files (which need differentcomment types.) Finally Greg ran the script using the .csv files togenerate the patches.Reviewed-by: Kate Stewart Reviewed-by: Philippe Ombredanne Reviewed-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/clk/tegra/Makefile

ca6f2796 - clk: tegra: Add BPMP clock driver

Thu, 17 Nov 2016 15:47:31 +0000

clk: tegra: Add BPMP clock driverThis driver uses the services provided by the BPMP firmware driver toimplement a clock driver based on the MRQ_CLK request. This part of theBPMP ABI provides a means to enumerate and control clocks and shouldallow the driver to work on any chip that supports this ABI.Signed-off-by: Thierry Reding Signed-off-by: Stephen Boyd List of files: /linux-6.15/drivers/clk/tegra/Makefile

1ec7032a - clk: tegra: Add fixed factor peripheral clock type

Mon, 20 Apr 2015 12:34:57 +0000

clk: tegra: Add fixed factor peripheral clock typeSome of the peripheral clocks on Tegra are derived from one of the top-level PLLs with a fixed factor. Support these clocks by implementing the->enable() and ->disable() callbacks using the peripheral clock registerbanks and the ->recalc_rate() by dividing the parent rate by the fixedfactor.Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

6b301a05 - clk: tegra: Add support for Tegra210 clocks

Thu, 18 Jun 2015 21:28:36 +0000

clk: tegra: Add support for Tegra210 clocksImplement clock support for Tegra210.Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

62a8a094 - clk: tegra: Add Tegra124 DFLL clocksource platform driver

Wed, 13 May 2015 14:58:41 +0000

clk: tegra: Add Tegra124 DFLL clocksource platform driverAdd basic platform driver support for the fast CPU cluster DFLLclocksource found on Tegra124 SoCs. This small driver selects theappropriate Tegra124-specific characterization data and integrationcode. It relies on the DFLL common code to do most of the work.Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette [treding@nvidia.com: move setup code into ->probe()]Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

d8d7a08f - clk: tegra: Add library for the DFLL clock source (open-loop mode)

Wed, 13 May 2015 14:58:36 +0000

clk: tegra: Add library for the DFLL clock source (open-loop mode)Add shared code to support the Tegra DFLL clocksource in open-loopmode. This root clocksource is present on the Tegra124 SoCs. TheDFLL is the intended primary clock source for the fast CPU cluster.This code is very closely based on a patch by Paul Walmsley fromDecember (http://comments.gmane.org/gmane.linux.ports.tegra/15273),which in turn comes from the internal driver by originally createdby Aleksandr Frid .Subsequent patches will add support for closed loop mode and driversfor the Tegra124 fast CPU cluster DFLL devices, which rely on thiscode.Signed-off-by: Paul Walmsley Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen Acked-by: Peter De Schrijver Acked-by: Michael Turquette Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

31b52ba4 - clk: tegra: EMC clock driver depends on EMC driver

Wed, 01 Apr 2015 07:10:58 +0000

clk: tegra: EMC clock driver depends on EMC driverThe EMC clock driver uses symbols exported by the EMC driver, so itneeds the corresponding dependency to avoid build breakage.Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

2db04f16 - clk: tegra: Add EMC clock driver

Thu, 12 Mar 2015 14:48:05 +0000

clk: tegra: Add EMC clock driverThe driver is currently only tested on Tegra124 Jetson TK1, but shouldwork with other Tegra124 boards, provided that correct EMC tables areprovided through the device tree. Older chip models have differingtiming change sequences, so they are not currently supported.Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso [treding@nvidia.com: use more consistent function names]Signed-off-by: Thierry Reding List of files: /linux-6.15/drivers/clk/tegra/Makefile

08acae34 - clk: tegra: Add support for the Tegra132 CAR IP block

Tue, 16 Dec 2014 20:38:29 +0000

clk: tegra: Add support for the Tegra132 CAR IP blockTegra132 CAR supports almost the same clocks as Tegra124 CAR. Thispatch mostly deals with the small differences.Since Tegra132 contains many of the same PLL clock sources used onTegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c whenthe kernel is configured to include Tegra132 support.This patch is based on several patches from others:1. a patch from Peter De Schrijver:http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot onTegra132"), and3. a patch from Allen Martin ("clk: Enable tegra clock driver fortegra132").Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Peter De Schrijver Cc: Allen Martin Cc: Prashant Gaikwad Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: Bill Huang Cc: Mike Turquette Cc: Stephen Boyd List of files: /linux-6.15/drivers/clk/tegra/Makefile

76da314d - clk: tegra124: Add support for Tegra124 clocks

Mon, 09 Sep 2013 10:23:56 +0000

clk: tegra124: Add support for Tegra124 clocksImplement clock support for Tegra124.Signed-off-by: Peter De Schrijver List of files: /linux-6.15/drivers/clk/tegra/Makefile