Changes in Makefile

ec8f24b7 - treewide: Add SPDX license identifier - Makefile/Kconfig

Sun, 19 May 2019 12:07:45 +0000

treewide: Add SPDX license identifier - Makefile/KconfigAdd SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any formThese files fall under the project license, GPL v2 only. The resulting SPDXlicense identifier is: GPL-2.0-onlySigned-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/clk/st/Makefile

b1165170 - clk: st: STiH407: Support for Flexgen Clocks

Tue, 15 Jul 2014 15:20:22 +0000

clk: st: STiH407: Support for Flexgen ClocksThis patch is the Flexgen implementation reusing as much as possibleof Common Clock Framework functions.The idea is to have an instance of "struct flexgen" per output clock.It represents the clock cross bar (by a mux element), and the pre and final dividers(using dividers and gates elements).Signed-off-by: Maxime Coquelin Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin Signed-off-by: Mike Turquette List of files: /linux-6.15/drivers/clk/st/Makefile

5f7aa907 - clk: st: Support for QUADFS inside ClockGenB/C/D/E/F

Thu, 27 Feb 2014 15:24:17 +0000

clk: st: Support for QUADFS inside ClockGenB/C/D/E/FThe patch supports the 216/432/660 type Quad Frequency Synthesizersused by ClockGenB/C/D/E/FQUADFS clock : It includes support for all 216/432/660 type QuadFrequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock,with clock rate calculated reading H/w settings done at BOOT.QuadFS have 4 outputs : chan0 chan1 chan2 chan3Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette List of files: /linux-6.15/drivers/clk/st/Makefile

b9b8e614 - clk: st: Support for PLLs inside ClockGenA(s)

Thu, 27 Feb 2014 15:24:15 +0000

clk: st: Support for PLLs inside ClockGenA(s)The patch supports the c65/c32 type PLLs used by ClockGenA(s)PLL clock : It includes support for all c65/c32 type PLLsinside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock,with clock rate calculated reading H/w settings done at BOOT.c65 PLLs have 2 outputs : HS and LSc32 PLLs have 1-4 outputs : ODFxSigned-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette List of files: /linux-6.15/drivers/clk/st/Makefile

94885faf - clk: st: Support for DIVMUX and PreDiv Clocks

Thu, 27 Feb 2014 15:24:14 +0000

clk: st: Support for DIVMUX and PreDiv ClocksThe patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s)DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s)It includes support for each channel : 3-parent Multiplexer,Divider for each Parent, Gate to switch OFF the output channel. Theclock is implemented using generic clocks implemented in the kernelclk_divider and clk_mux.PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to dividethe oscillator clock by factor-of-16. The clock is implemented usinggeneric clocks implemented in the kernel clk_divider.Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette List of files: /linux-6.15/drivers/clk/st/Makefile