Changes in Makefile

bb6a9aaf - clk: renesas: rzv2h: Add support for RZ/G3E SoC

Fri, 13 Dec 2024 12:35:41 +0000

clk: renesas: rzv2h: Add support for RZ/G3E SoCThe clock structure for RZ/G3E is almost identical to RZ/V2H SoC withmore IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1are present only on the RZ/G3E SoC.Add minimal clock and reset entries required to boot the Renesas RZ/G3ESMARC EVK and binds it with the RZ/V2H CPG core driver.Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

3b42450c - clk: renesas: vbattb: Add VBATTB clock driver

Fri, 01 Nov 2024 09:57:14 +0000

clk: renesas: vbattb: Add VBATTB clock driverThe VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is usedby the RTC. The input to the VBATTB could be a 32KHz crystalor an external clock device.The HW block diagram for the clock generator is as follows: +----------+ XC `\RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+RTXOUT --->| |----->| / +----------+ ,After discussions w/ Stephen Boyd the clock tree associated with thishardware block was exported in Linux as:vbattb-xtal xbyp xc mux vbattbclkwhere:- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)- xc, xbyp are mux inputs- mux is the internal mux- vbattclk is the gate clock that feeds in the end the RTCto allow selecting the input of the MUX though assigned-clock DTproperties, using the already existing clock drivers and avoid addingother DT properties. If the crystal is connected on RTXIN,RTXOUT pins the XC will be selected as mux input. If an external clockdevice is connected on RTXIN, RTXOUT pins the XBYP will be selected asmux input.The load capacitance of the internal crystal can be configuredwith renesas,vbattb-load-nanofarads DT property.Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

36932cbc - clk: renesas: Add RZ/V2H(P) CPG driver

Mon, 29 Jul 2024 20:26:45 +0000

clk: renesas: Add RZ/V2H(P) CPG driverAdd RZ/V2H(P) CPG driver.Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240729202645.263525-4-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

dd22e562 - clk: renesas: Add family-specific clock driver for RZ/V2H(P)

Mon, 29 Jul 2024 20:26:44 +0000

clk: renesas: Add family-specific clock driver for RZ/V2H(P)Add family-specific clock driver for RZ/V2H(P) SoCs.Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240729202645.263525-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

f077cab3 - clk: renesas: cpg-mssr: Add support for R-Car V4M

Thu, 25 Jan 2024 15:34:36 +0000

clk: renesas: cpg-mssr: Add support for R-Car V4MInitial CPG support for the R-Car V4M (R8A779H0).Signed-off-by: Cong Dang Signed-off-by: Geert Uytterhoeven Acked-by: Niklas Söderlund Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be List of files: /linux-6.15/drivers/clk/renesas/Makefile

de60a3eb - clk: renesas: Add minimal boot support for RZ/G3S SoC

Fri, 06 Oct 2023 10:39:59 +0000

clk: renesas: Add minimal boot support for RZ/G3S SoCAdd minimal clock and reset support for the RZ/G3S SoC to be able toboot Linux from SD Card/eMMC. This includes necessary core clocks forbooting and GIC, SCIF, GPIO, and SD0 module clocks and resets.Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

1dd65bb0 - clk: renesas: Add RZ/V2M support using the rzg2l driver

Tue, 03 May 2022 11:55:55 +0000

clk: renesas: Add RZ/V2M support using the rzg2l driverThe Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't haveany CLK_MON registers.Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

0ab55cf1 - clk: renesas: cpg-mssr: Add support for R-Car V4H

Thu, 28 Apr 2022 13:50:56 +0000

clk: renesas: cpg-mssr: Add support for R-Car V4HInitial CPG support for R-Car V4H (r8a779g0).Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

c8b08822 - clk: renesas: Add support for RZ/G2UL SoC

Tue, 12 Apr 2022 16:13:12 +0000

clk: renesas: Add support for RZ/G2UL SoCThe clock structure for RZ/G2UL is almost identical to RZ/G2L SoC withfewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG arenot present on RZ/G2UL.This patch adds minimal clock and reset entries required to boot thesystem on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG coredriver.Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

a1bcf50a - clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

Sat, 05 Feb 2022 08:40:06 +0000

clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCThe clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.The only difference being that RZ/V2L has additional registers tocontrol clocks and resets for the DRP-AI block.Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the samebetween RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to takecare of the DRP-AI clocks/resets.Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.comLink: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

24aaff6a - clk: renesas: cpg-mssr: Add support for R-Car S4-8

Wed, 01 Dec 2021 07:33:03 +0000

clk: renesas: cpg-mssr: Add support for R-Car S4-8Initial CPG support for R-Car S4-8 (r8a779f0).Inspired by patches in the BSP by LUU HOAI.Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

470e3f0d - clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver

Wed, 01 Dec 2021 07:33:02 +0000

clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverAccording to the official website [1], the R-Car V3U SoC is basedon the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPGdriver.[1]https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-drivingSigned-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

0aae437a - clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]

Wed, 14 Jul 2021 13:26:01 +0000

clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Rename renesas-rzg2l-cpg.c and renesas-rzg2l-cpg.h to rzg2l-cpg.c resp.rzg2l-cpg.h, for consistency with other (sub)drivers.Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Acked-by: Biju Das Link: https://lore.kernel.org/r/edc442daaedffcf10e835ff479d906fcae0e59db.1626268821.git.geert+renesas@glider.be List of files: /linux-6.15/drivers/clk/renesas/Makefile

17f0ff3d - clk: renesas: Add support for R9A07G044 SoC

Wed, 09 Jun 2021 15:32:28 +0000

clk: renesas: Add support for R9A07G044 SoCDefine the clock outputs supported by RZ/G2L (R9A07G044) SoCand bind it with RZ/G2L CPG core.Based on a patch in the BSP by Binh Nguyen.Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

ef3c613c - clk: renesas: Add CPG core wrapper for RZ/G2L SoC

Wed, 09 Jun 2021 15:32:27 +0000

clk: renesas: Add CPG core wrapper for RZ/G2L SoCAdd CPG core wrapper for RZ/G2L family.Based on a patch in the BSP by Binh Nguyen.Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

8bb67d87 - clk: renesas: rcar-gen3: Factor out CPG library

Sun, 27 Dec 2020 17:41:57 +0000

clk: renesas: rcar-gen3: Factor out CPG libraryR-Car V3U has a CPG different enough to not be a generic Gen3 CPG butsimilar enough to reuse code. Introduce a new CPG library, factor outthe SD clock handling and hook it to the generic Gen3 CPG driver so wehave an equal state. V3U will make use of it in the next patch then.Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

17bcc803 - clk: renesas: cpg-mssr: Add support for R-Car V3U

Fri, 11 Sep 2020 07:43:51 +0000

clk: renesas: cpg-mssr: Add support for R-Car V3UInitial support for R-Car V3U (r8a779a0), including core, moduleclocks, resets, and register access, because register specificationdiffers from R-Car Gen2/3.Inspired by patches in the BSP by LUU HOAI.Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

c8a53fa1 - clk: renesas: cpg-mssr: Add r8a774e1 support

Tue, 07 Jul 2020 16:18:10 +0000

clk: renesas: cpg-mssr: Add r8a774e1 supportAdd support for the RZ/G2H (R8A774E1) SoC to the Renesas ClockPulse Generator / Module Standby and Software Reset driver.Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com[geert: Mark RWDT critical, cfr. commit f23f1101ad0ef1ac ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")]Signed-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

e8208a71 - clk: renesas: cpg-mssr: Add R8A7742 support

Mon, 27 Apr 2020 14:41:00 +0000

clk: renesas: cpg-mssr: Add R8A7742 supportAdd RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and SoftwareReset support, using the CPG/MSSR driver core and the common R-Car Gen2(and RZ/G) code.Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/clk/renesas/Makefile

2ba738d5 - clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support

Wed, 23 Oct 2019 12:29:41 +0000

clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportAdd support for the R-Car M3-W+ (R8A77961) SoC to the Renesas ClockPulse Generator / Module Standby and Software Reset driver.R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows forboth SoCs to share a driver. R-Car M3-W+ lacks a few modules, so theirclocks must be nullified.Based on a patch in the BSP by Takeshi Kihara.Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20191023122941.12342-5-geert+renesas@glider.be List of files: /linux-6.15/drivers/clk/renesas/Makefile