6f3b1558 - clk: ralink: add clock and reset driver for MTMIPS SoCs

Mon, 19 Jun 2023 04:09:34 +0000

clk: ralink: add clock and reset driver for MTMIPS SoCsUntil now, clock related code for old ralink SoCs was based in fixed clocksusing 'clk_register_fixed_rate' and 'clkdev_create' directly doing in codeand not using device tree at all for their definition. Including this driveris an effort to be able to define proper clocks using device tree and alsocleaning all the clock and reset related code from 'arch/mips/ralink' dir.This clock and reset driver covers all the ralink SoCs but MT7621 which isthe newest and provides gating and some differences that make it differentfrom its predecesors. It has its own driver since some time ago. The ralinkSoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver hasbeen extracted from 'arch/mips/ralink' and cleanly put using kernel clockdriver APIs. The clock plans for this SoCs only talks about relation betweenCPU frequency and BUS frequency. This relation is different depending on theparticular SoC. CPU clock is derived from XTAL frequencies.Depending on the SoC we have the following frequencies:* RT2880 SoC: - XTAL: 40 MHz. - CPU: 250, 266, 280 or 300 MHz. - BUS: CPU / 2 MHz.* RT3050, RT3052, RT3350: - XTAL: 40 MHz. - CPU: 320 or 384 MHz. - BUS: CPU / 3 MHz.* RT3352: - XTAL: 40 MHz. - CPU: 384 or 400 MHz. - BUS: CPU / 3 MHz. - PERIPH: 40 MHz.* RT3383: - XTAL: 40 MHz. - CPU: 250, 384, 480 or 500 MHz. - BUS: Depends on RAM Type and CPU: + RAM DDR2: 125. ELSE 83 MHz. + RAM DDR2: 128. ELSE 96 MHz. + RAM DDR2: 160. ELSE 120 MHz. + RAM DDR2: 166. ELSE 125 MHz.* RT5350: - XTAL: 40 MHz. - CPU: 300, 320 or 360 MHz. - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. - PERIPH: 40 MHz.* MT7628 and MT7688: - XTAL: 20 MHz or 40 MHz. - CPU: 575 or 580 MHz. - BUS: CPU / 3. - PCMI2S: 480 MHz. - PERIPH: 40 MHz.* MT7620: - XTAL: 20 MHz or 40 MHz. - PLL: XTAL, 480, 600 MHz. - CPU: depends on PLL and some mult and dividers. - BUS: depends on PLL and some mult and dividers. - PERIPH: 40 or XTAL MHz.MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch ofregister reads and predividers. To derive CPU and BUS frequencies in theMT7620 SoC 'mt7620_calc_rate()' helper is used.In the case XTAL can have different frequencies and we need a differentclock frequency for peripherals 'periph' clock in introduced.The rest of the peripherals present in the SoC just follow their parentfrequencies.With this information the clk driver will provide all the clock and resetfunctionality from a set of hardcoded clocks allowing to define a nicedevice tree without fixed clocks.Acked-by: Stephen Boyd Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer List of files: /linux-6.15/drivers/clk/ralink/Makefile

48df7a26 - clk: ralink: add clock driver for mt7621 SoC

Sat, 10 Apr 2021 05:50:56 +0000

clk: ralink: add clock driver for mt7621 SoCThe documentation for this SOC only talks about tworegisters regarding to the clocks:* SYSC_REG_CPLL_CLKCFG0 - provides some information aboutboostrapped refclock. PLL and dividers used for CPU and somesort of BUS.* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disableclocks for all or some ip cores.Looking into driver code, and some openWRT patched there areanother frequencies which are used in some drivers (uart, sd...).According to all of this information the clock plan for thisSoC is set as follows:- Main top clock "xtal" from where all the rest of the world isderived.- CPU clock "cpu" derived from "xtal" frequencies and a bunch ofregister reads and predividers.- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.- Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz.We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m"With this information the clk driver will provide clock and gatesfunctionality from a a set of hardcoded clocks allowing to definea nice device tree without fixed clocks.Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.comSigned-off-by: Stephen Boyd List of files: /linux-6.15/drivers/clk/ralink/Makefile

Changes in Makefile

6f3b1558 - clk: ralink: add clock and reset driver for MTMIPS SoCs

48df7a26 - clk: ralink: add clock driver for mt7621 SoC