691521a3 - clk: nuvoton: Add clock driver for ma35d1 clock controller

Mon, 05 Jun 2023 04:07:47 +0000

clk: nuvoton: Add clock driver for ma35d1 clock controllerThe clock controller generates clocks for the whole chip, includingsystem clocks and all peripheral clocks. This driver support ma35d1clock gating, divider, and individual PLL configuration.There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs.CA-PLL has only one operation mode.DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3operation modes: integer mode, fraction mode, and spread specturm mode.Signed-off-by: Jacky Huang Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann List of files: /linux-6.15/drivers/clk/nuvoton/Makefile

Changes in Makefile

691521a3 - clk: nuvoton: Add clock driver for ma35d1 clock controller