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    <title>Changes in Makefile</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>ec8f24b7 - treewide: Add SPDX license identifier - Makefile/Kconfig</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#ec8f24b7</link>
        <description>treewide: Add SPDX license identifier - Makefile/KconfigAdd SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any formThese files fall under the project license, GPL v2 only. The resulting SPDXlicense identifier is:  GPL-2.0-onlySigned-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Sun, 19 May 2019 12:07:45 +0000</pubDate>
        <dc:creator>Thomas Gleixner &lt;tglx@linutronix.de&gt;</dc:creator>
    </item>
<item>
        <title>18882ac5 - clk: berlin: add core clock driver for BG2Q</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#18882ac5</link>
        <description>clk: berlin: add core clock driver for BG2QThis driver deals with the core clocks found on Marvell Berlin BG2Q. For theshared register dividers, make use of the corresponding driver and add somesingle clock muxes and gates for the rest.Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Mon, 19 May 2014 16:43:28 +0000</pubDate>
        <dc:creator>Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;</dc:creator>
    </item>
<item>
        <title>ba0fae3b - clk: berlin: add core clock driver for BG2/BG2CD</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#ba0fae3b</link>
        <description>clk: berlin: add core clock driver for BG2/BG2CDThis driver deals with the core clocks found on Marvell BerlinBG2 and BG2CD. For the shared register dividers, make use of thecorresponding driver and add some single clock muxes and gates forthe rest.Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;Acked-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Mon, 19 May 2014 16:43:27 +0000</pubDate>
        <dc:creator>Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;</dc:creator>
    </item>
<item>
        <title>6f9ba9b4 - clk: berlin: add driver for BG2x complex divider cells</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#6f9ba9b4</link>
        <description>clk: berlin: add driver for BG2x complex divider cellsThis is a driver for the complex divider cells found on Marvell Berlin2SoCs. The cells come in two flavors: single register cells and sharedregister cells.Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Mon, 19 May 2014 16:43:26 +0000</pubDate>
        <dc:creator>Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;</dc:creator>
    </item>
<item>
        <title>cf8de5a7 - clk: berlin: add driver for BG2x simple PLLs</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#cf8de5a7</link>
        <description>clk: berlin: add driver for BG2x simple PLLsThis is a clock driver for the simple PLLs found on Berlin SoCs.With repect to PLL registers and features, BG2/BG2CD and BG2Q areslightly different, e.g. different allowed VCO dividers and bitshifts.Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Mon, 19 May 2014 16:43:25 +0000</pubDate>
        <dc:creator>Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;</dc:creator>
    </item>
<item>
        <title>beca8ccc - clk: berlin: add driver for BG2x audio/video PLL</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/drivers/clk/berlin/Makefile#beca8ccc</link>
        <description>clk: berlin: add driver for BG2x audio/video PLLThis is a driver for the AVPLLs built upon a VCO with 8 channels eachfound on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD sharethe same register set, sometimes registers shifts for one of the VCOsare a bit off. Nothing serious that should require a separate driver,so deal with both VCOs in a single driver instead.Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;

            List of files:
            /linux-6.15/drivers/clk/berlin/Makefile</description>
        <pubDate>Mon, 19 May 2014 16:43:24 +0000</pubDate>
        <dc:creator>Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;</dc:creator>
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