Changes in Kconfig

57e5c814 - cache: StarFive: Require a 64-bit system

Mon, 22 Jul 2024 15:45:20 +0000

cache: StarFive: Require a 64-bit systemThis has a bunch of {read,write}q() calls, so it won't work on 32-bitsystems. I don't think there's any 32-bit StarFive systems, so for nowjust require 64-bit.Fixes: cabff60ca77d ("cache: Add StarFive StarLink cache management")Acked-by: Conor Dooley Reviewed-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20240722154519.25375-2-palmer@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/drivers/cache/Kconfig

cabff60c - cache: Add StarFive StarLink cache management

Wed, 15 May 2024 05:02:52 +0000

cache: Add StarFive StarLink cache managementAdd StarFive Starlink cache management driver.The driver enables RISC-V non-standard cacheoperation on SoC that does not support Zicbomextension instructions.Signed-off-by: Joshua Yeong Signed-off-by: Conor Dooley List of files: /linux-6.15/drivers/cache/Kconfig

971f128b - soc: sifive: shunt ccache driver to drivers/cache

Thu, 12 Oct 2023 09:22:09 +0000

soc: sifive: shunt ccache driver to drivers/cacheMove the ccache driver over to drivers/cache, out of the drivers/socdumping ground, to this new collection point for cache controllerdrivers.Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Conor Dooley List of files: /linux-6.15/drivers/cache/Kconfig

fd962781 - riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT

Wed, 18 Oct 2023 05:26:52 +0000

riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENTRISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenancehelpers, which are built into the kernel unconditionally.Signed-off-by: Christoph Hellwig Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.deSigned-off-by: Geert Uytterhoeven List of files: /linux-6.15/drivers/cache/Kconfig

d34599bc - cache: Add L2 cache management for Andes AX45MP RISC-V core

Fri, 18 Aug 2023 13:57:22 +0000

cache: Add L2 cache management for Andes AX45MP RISC-V coreI/O Coherence Port (IOCP) provides an AXI interface for connectingexternal non-caching masters, such as DMA controllers. The accessesfrom IOCP are coherent with D-Caches and L2 Cache.IOCP is a specification option and is disabled on the Renesas RZ/FiveSoC due to this reason IP blocks using DMA will fail.The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)block that allows dynamic adjustment of memory attributes in the runtime.It contains a configurable amount of PMA entries implemented as CSRregisters to control the attributes of memory locations in interest.Below are the memory attributes supported:* Device, Non-bufferable* Device, bufferable* Memory, Non-cacheable, Non-bufferable* Memory, Non-cacheable, Bufferable* Memory, Write-back, No-allocate* Memory, Write-back, Read-allocate* Memory, Write-back, Write-allocate* Memory, Write-back, Read and Write-allocateMore info about PMA (section 10.3):Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdfAs a workaround for SoCs with IOCP disabled CMO needs to be handled bysoftware. Firstly OpenSBI configures the memory region as"Memory, Non-cacheable, Bufferable" and passes this region as a globalshared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMAallocations happen from this region and synchronization callbacks areimplemented to synchronize when doing DMA transactions.Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; };Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/drivers/cache/Kconfig