Changes in intel_epb.c

fe3edc52 - x86/cpu/intel_epb: Switch to new Intel CPU model defines

Wed, 24 Apr 2024 18:15:09 +0000

x86/cpu/intel_epb: Switch to new Intel CPU model definesNew CPU #defines encode vendor and family as well as model.Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/all/20240424181510.41733-1-tony.luck%40intel.com List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

d87c4937 - x86: intel_epb: Don't rely on link order

Tue, 21 Nov 2023 13:44:00 +0000

x86: intel_epb: Don't rely on link orderintel_epb_init() is called as a subsys_initcall() to register cpuhpcallbacks. The callbacks make use of get_cpu_device() which will returnNULL unless register_cpu() has been called. register_cpu() is calledfrom topology_init(), which is also a subsys_initcall().This is fragile. Moving the register_cpu() to a differentsubsys_initcall() leads to a NULL dereference during boot.Make intel_epb_init() a late_initcall(), user-space can't provide apolicy before this point anyway.Signed-off-by: James Morse Reviewed-by: Gavin Shan Signed-off-by: "Russell King (Oracle)" Acked-by: "Rafael J. Wysocki" Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/E1r5R2m-00Csyb-2S@rmk-PC.armlinux.org.ukSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

5bfa0e45 - x86/cpu/intel_epb: Don't rely on link order

Fri, 24 Nov 2023 09:38:53 +0000

x86/cpu/intel_epb: Don't rely on link orderintel_epb_init() is called as a subsys_initcall() to register cpuhpcallbacks. The callbacks make use of get_cpu_device() which will returnNULL unless register_cpu() has been called. register_cpu() is calledfrom topology_init(), which is also a subsys_initcall().This is fragile. Moving the register_cpu() to a differentsubsys_initcall() leads to a NULL dereference during boot.Make intel_epb_init() a late_initcall(), user-space can't provide apolicy before this point anyway.Signed-off-by: James Morse Signed-off-by: Russell King (Oracle) Signed-off-by: Ingo Molnar Reviewed-by: Gavin Shan Acked-by: Rafael J. Wysocki List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

882cdb06 - x86/cpu: Fix Gracemont uarch

Mon, 07 Aug 2023 12:38:07 +0000

x86/cpu: Fix Gracemont uarchAlderlake N is an E-core only product using Gracemontmicro-architecture. It fits the pre-existing naming scheme perfectlyfine, adhere to it.Signed-off-by: Peter Zijlstra (Intel) Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

7420ae3b - x86/intel_epb: Set Alder Lake N and Raptor Lake P normal EPB

Thu, 27 Oct 2022 22:00:56 +0000

x86/intel_epb: Set Alder Lake N and Raptor Lake P normal EPBIntel processors support additional software hint called EPB ("EnergyPerformance Bias") to guide the hardware heuristic of power managementfeatures to favor increasing dynamic performance or conserve energyconsumption.Since this EPB hint is processor specific, the same value of hint canresult in different behavior across generations of processors.commit 4ecc933b7d1f ("x86: intel_epb: Allow model specific normal EPBvalue")' introduced capability to update the default power up EPBbased on the CPU model and updated the default EPB to 7 for Alder Lakemobile CPUs.The same change is required for other Alder Lake-N and Raptor Lake-Pmobile CPUs as the current default of 6 results in higher uncore powerconsumption. This increase in power is related to memory clockfrequency setting based on the EPB value.Depending on the EPB the minimum memory frequency is set by thefirmware. At EPB = 7, the minimum memory frequency is 1/4th compared toEPB = 6. This results in significant power saving for idle andsemi-idle workload on a Chrome platform.For example Change in power and performance from EPB change from 6 to 7on Alder Lake-N:Workload Performance diff (%) power diff----------------------------------------------------VP9 FHD30 0 (FPS) -218 mwGoogle meet 0 (FPS) -385 mwThis 200+ mw power saving is very significant for mobile platform forbattery life and thermal reasons.But as the workload demands more memory bandwidth, the memory frequencywill be increased very fast. There is no power savings for such busyworkloads.For example:Workload Performance diff (%) from EPB 6 to 7-------------------------------------------------------Speedometer 2.0 -0.8WebGL Aquarium 10KFish -0.5Unity 3D 2018 0.2WebXPRT3 -0.5There are run to run variations for performance scores forsuch busy workloads. So the difference is not significant.Add a new define ENERGY_PERF_BIAS_NORMAL_POWERSAVE for EPB 7and use it for Alder Lake-N and Raptor Lake-P mobile CPUs.This modification is done originally byJeremy Compostella .Signed-off-by: Srinivas Pandruvada Signed-off-by: Dave Hansen Reviewed-by: Rafael J. Wysocki Link: https://lore.kernel.org/all/20221027220056.1534264-1-srinivas.pandruvada%40linux.intel.com List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

4ecc933b - x86: intel_epb: Allow model specific normal EPB value

Sat, 11 Dec 2021 16:33:27 +0000

x86: intel_epb: Allow model specific normal EPB valueThe current EPB "normal" is defined as 6 and set whenever power-up EPBvalue is 0. This setting resulted in the desired out of box power andperformance for several CPU generations. But this value is not suitablefor AlderLake mobile CPUs, as this resulted in higher uncore power.Since EPB is model specific, this is not unreasonable to have differentbehavior.Allow a capability where "normal" EPB can be redefined. For AlderLakemobile CPUs this desired normal value is 7.Signed-off-by: Srinivas Pandruvada Signed-off-by: Rafael J. Wysocki List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

be1fcde6 - x86: intel_epb: Do not build when CONFIG_PM is unset

Mon, 27 May 2019 10:56:07 +0000

x86: intel_epb: Do not build when CONFIG_PM is unsetCommit 9ed0985332a6 ("x86: intel_epb: Take CONFIG_PM into account")prevented the majority of the Performance and Energy Bias Hint (EPB)handling code from being built when CONFIG_PM is unset to fix aregression introduced by commit b9c273babce7 ("PM / arch: x86:MSR_IA32_ENERGY_PERF_BIAS sysfs interface").In hindsight, however, it would be better to skip all of the EPBhandling code for CONFIG_PM unset as there really is no reason forit to be there in that case. Namely, if the EPB is not touchedby the kernel at all with CONFIG_PM unset, there is no need toworry about modifying the EPB inadvertently on CPU online and sincethe system will not suspend or hibernate then, there is no need toworry about possible modifications of the EPB by the platformfirmware during system-wide PM transitions.For this reason, revert the changes made by commit 9ed0985332a6and only allow intel_epb.o to be built when CONFIG_PM is set.Note that this changes the behavior of the kernels built withCONFIG_PM unset as they will not modify the EPB on boot if it iszero initially any more, so it is not a fix strictly speaking, butusers building their kernels with CONFIG_PM unset really should notexpect them to take energy efficiency into account. Moreover, ifCONFIG_PM is unset for performance reasons, leaving EPB as setinitially by the platform firmware will actually be consistentwith the user's expectations.Signed-off-by: Rafael J. Wysocki Acked-by: Ingo Molnar List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

9ed09853 - x86: intel_epb: Take CONFIG_PM into account

Thu, 09 May 2019 21:28:41 +0000

x86: intel_epb: Take CONFIG_PM into accountCommit b9c273babce7 ("PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfsinterface") caused kernels built with CONFIG_PM unset to crash onsystems supporting the Performance and Energy Bias Hint (EPB),because it attempts to add files to sysfs directories that don'texist on those systems.Prevent that from happening by taking CONFIG_PM into account sothat the code depending on it is not compiled at all when it isnot set.Fixes: b9c273babce7 ("PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfs interface")Reported-by: Ido Schimmel Tested-by: Ido Schimmel Signed-off-by: Rafael J. Wysocki Acked-by: Ingo Molnar List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

b9c273ba - PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfs interface

Thu, 21 Mar 2019 22:20:17 +0000

PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfs interfaceThe Performance and Energy Bias Hint (EPB) is expected to be set byuser space through the generic MSR interface, but that interface isnot particularly nice and there are security concerns regarding it,so it is not always available.For this reason, add a sysfs interface for reading and updating theEPB, in the form of a new attribute, energy_perf_bias, locatedunder /sys/devices/system/cpu/cpu#/power/ for online CPUs thatsupport the EPB feature.Signed-off-by: Rafael J. Wysocki Reviewed-by: Hannes Reinecke Acked-by: Borislav Petkov List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c

5861381d - PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handling

Thu, 21 Mar 2019 22:18:01 +0000

PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handlingThe current handling of MSR_IA32_ENERGY_PERF_BIAS in the kernel isproblematic, because it may cause changes made by user space to thatMSR (with the help of the x86_energy_perf_policy tool, for example)to be lost every time a CPU goes offline and then back online as wellas during system-wide power management transitions into sleep statesand back into the working state.The first problem is that if the current EPB value for a CPU goingonline is 0 ('performance'), the kernel will change it to 6 ('normal')regardless of whether or not this is the first bring-up of that CPU.That also happens during system-wide resume from sleep states(including, but not limited to, hibernation). However, the EPB mayhave been adjusted by user space this way and the kernel should notblindly override that setting.The second problem is that if the platform firmware resets the EPBvalues for any CPUs during system-wide resume from a sleep state,the kernel will not restore their previous EPB values that mayhave been set by user space before the preceding system-widesuspend transition. Again, that behavior may at least be confusingfrom the user space perspective.In order to address these issues, rework the handling ofMSR_IA32_ENERGY_PERF_BIAS so that the EPB value is saved on CPUoffline and restored on CPU online as well as (for the boot CPU)during the syscore stages of system-wide suspend and resumetransitions, respectively.However, retain the policy by which the EPB is set to 6 ('normal')on the first bring-up of each CPU if its initial value is 0, basedon the observation that 0 may mean 'not initialized' just as well as'performance' in that case.While at it, move the MSR_IA32_ENERGY_PERF_BIAS handling code intoa separate file and document it in Documentation/admin-guide.Fixes: abe48b108247 (x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS)Fixes: b51ef52df71c (x86/cpu: Restore MSR_IA32_ENERGY_PERF_BIAS after resume)Reported-by: Thomas Renninger Signed-off-by: Rafael J. Wysocki Reviewed-by: Hannes Reinecke Acked-by: Borislav Petkov Acked-by: Thomas Gleixner List of files: /linux-6.15/arch/x86/kernel/cpu/intel_epb.c