Changes in Makefile

f9aad622 - mm: rename GENERIC_PTDUMP and PTDUMP_CORE

Wed, 26 Feb 2025 12:24:04 +0000

mm: rename GENERIC_PTDUMP and PTDUMP_COREPlatforms subscribe into generic ptdump implementation via GENERIC_PTDUMP.But generic ptdump gets enabled via PTDUMP_CORE. These configscombination is confusing as they sound very similar and does notdifferentiate between platform's feature subscription and featureenablement for ptdump. Rename the configs as ARCH_HAS_PTDUMP and PTDUMPmaking it more clear and improve readability.Link: https://lkml.kernel.org/r/20250226122404.1927473-6-anshuman.khandual@arm.comSigned-off-by: Anshuman Khandual Reviewed-by: Christophe Leroy (powerpc)Acked-by: Catalin Marinas [arm64]Cc: Will Deacon Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Heiko Carstens Cc: Vasily Gorbik Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Christophe Leroy Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Steven Price Signed-off-by: Andrew Morton List of files: /linux-6.15/arch/riscv/mm/Makefile

c6026d35 - riscv: mm: Combine the SMP and UP TLB flush code

Wed, 27 Mar 2024 04:49:47 +0000

riscv: mm: Combine the SMP and UP TLB flush codeIn SMP configurations, all TLB flushing narrower than flush_tlb_all()goes through __flush_tlb_range(). Do the same in UP configurations.This allows UP configurations to take advantage of recent improvementsto the code in tlbflush.c, such as support for huge pages and flushingmultiple-page ranges.Reviewed-by: Alexandre Ghiti Signed-off-by: Samuel Holland Reviewed-by: Yunhui Cui Link: https://lore.kernel.org/r/20240327045035.368512-7-samuel.holland@sifive.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

d6508999 - riscv: mm: Only compile pgtable.c if MMU

Wed, 13 Dec 2023 20:30:00 +0000

riscv: mm: Only compile pgtable.c if MMUAll functions defined in there depend on MMU, so no need to compile itfor !MMU configs.Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20231213203001.179237-4-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

946bb33d - riscv: split cache ops out of dma-noncoherent.c

Sat, 28 Oct 2023 15:51:01 +0000

riscv: split cache ops out of dma-noncoherent.cThe cache ops are also used by the pmem code which is unconditionallybuilt into the kernel. Move them into a separate file that is builtbased on the correct config option.Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT")Reported-by: kernel test robot Signed-off-by: Christoph Hellwig Reviewed-by: Conor Dooley Tested-by: Conor Dooley Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar #Link: https://lore.kernel.org/r/20231028155101.1039049-1-hch@lst.deSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

de658bcf - riscv: mm: stub extable related functions/macros for !MMU

Tue, 09 May 2023 15:26:41 +0000

riscv: mm: stub extable related functions/macros for !MMUextable relies on the MMU to work properly, so it's useless toinclude __ex_table sections and build extable related functions for!MMU case.Signed-off-by: Jisheng Zhang Link: https://lore.kernel.org/r/20230509152641.805-1-jszhang@kernel.orgSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

39b33072 - riscv: Introduce CONFIG_RELOCATABLE

Wed, 29 Mar 2023 04:53:26 +0000

riscv: Introduce CONFIG_RELOCATABLEThis config allows to compile 64b kernel as PIE and to relocate it atany virtual address at runtime: this paves the way to KASLR.Runtime relocation is possible since relocation metadata are embedded intothe kernel.Note that relocating at runtime introduces an overhead even if thekernel is loaded at the same address it was linked at and that the compileroptions are those used in arm64 which uses the same RELA relocationformat.Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20230329045329.64565-4-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

a49ab905 - RISC-V: Implement arch specific PMEM APIs

Mon, 14 Nov 2022 09:05:35 +0000

RISC-V: Implement arch specific PMEM APIsThe NVDIMM PMEM driver expects arch specific APIs for cache maintenanceand if arch does not provide these APIs then NVDIMM PMEM driver willalways use MEMREMAP_WT to map persistent memory which in-turn maps asUC memory type defined by the RISC-V Svpbmt specification.Now that the Svpbmt and Zicbom support is available in RISC-V kernel,we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMMPMEM driver can use MEMREMAP_WB to map persistent memory.Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20221114090536.1662624-3-apatel@ventanamicro.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

310f541a - riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT

Wed, 12 Oct 2022 12:00:37 +0000

riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BITThis sets the HAVE_ARCH_HUGE_VMAP option, and defines the required pagetable functions. With this feature, ioremap area will be mapped withhuge page granularity according to its actual size. This feature can bedisabled by kernel parameter "nohugeiomap".Signed-off-by: Liu Shixin Reviewed-by: Björn Töpel Tested-by: Björn Töpel Link: https://lore.kernel.org/r/20221012120038.1034354-2-liushixin2@huawei.com[Palmer: minor formatting]Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

1631ba12 - riscv: Add support for non-coherent devices using zicbom extension

Wed, 06 Jul 2022 23:15:35 +0000

riscv: Add support for non-coherent devices using zicbom extensionThe Zicbom ISA-extension was ratified in november 2021and introduces instructions for dcache invalidate, cleanand flush operations.Implement cache management operations for non-coherent devicesbased on them.Of course not all cores will support this, so implement analternative-based mechanism that replaces empty instructionswith ones done around Zicbom instructions.As discussed in previous versions, assume the platformbeing coherent by default so that non-coherent devices needto get marked accordingly by firmware.Reviewed-by: Christoph Hellwig Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.deSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

c648c4bb - riscv: Fix config KASAN && DEBUG_VIRTUAL

Fri, 25 Feb 2022 12:39:51 +0000

riscv: Fix config KASAN && DEBUG_VIRTUAL__virt_to_phys function is called very early in the boot process (iekasan_early_init) so it should not be instrumented by KASAN otherwise itbugs.Fix this by declaring phys_addr.c as non-kasan instrumentable.Signed-off-by: Alexandre Ghiti Fixes: 8ad8b72721d0 (riscv: Add KASAN support)Cc: stable@vger.kernel.orgSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

5ad84adf - riscv: Fixup patch_text panic in ftrace

Thu, 17 Dec 2020 16:01:40 +0000

riscv: Fixup patch_text panic in ftraceJust like arm64, we can't trace the function in the patch_text path.Here is the bug log:[ 45.234334] Unable to handle kernel paging request at virtual address ffffffd38ae80900[ 45.242313] Oops [#1][ 45.244600] Modules linked in:[ 45.247678] CPU: 0 PID: 11 Comm: migration/0 Not tainted 5.9.0-00025-g9b7db83-dirty #215[ 45.255797] epc: ffffffe00021689a ra : ffffffe00021718e sp : ffffffe01afabb58[ 45.262955] gp : ffffffe00136afa0 tp : ffffffe01af94d00 t0 : 0000000000000002[ 45.270200] t1 : 0000000000000000 t2 : 0000000000000001 s0 : ffffffe01afabc08[ 45.277443] s1 : ffffffe0013718a8 a0 : 0000000000000000 a1 : ffffffe01afabba8[ 45.284686] a2 : 0000000000000000 a3 : 0000000000000000 a4 : c4c16ad38ae80900[ 45.291929] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000052464e43[ 45.299173] s2 : 0000000000000001 s3 : ffffffe000206a60 s4 : ffffffe000206a60[ 45.306415] s5 : 00000000000009ec s6 : ffffffe0013718a8 s7 : c4c16ad38ae80900[ 45.313658] s8 : 0000000000000004 s9 : 0000000000000001 s10: 0000000000000001[ 45.320902] s11: 0000000000000003 t3 : 0000000000000001 t4 : ffffffffd192fe79[ 45.328144] t5 : ffffffffb8f80000 t6 : 0000000000040000[ 45.333472] status: 0000000200000100 badaddr: ffffffd38ae80900 cause: 000000000000000f[ 45.341514] ---[ end trace d95102172248fdcf ]---[ 45.346176] note: migration/0[11] exited with preempt_count 1(gdb) x /2i $pc=> 0xffffffe00021689a <__do_proc_dointvec+196>: sd zero,0(s7) 0xffffffe00021689e <__do_proc_dointvec+200>: li s11,0(gdb) bt0 __do_proc_dointvec (tbl_data=0x0, table=0xffffffe01afabba8,write=0, buffer=0x0, lenp=0x7bf897061f9a0800, ppos=0x4, conv=0x0,data=0x52464e43) at kernel/sysctl.c:5811 0xffffffe00021718e in do_proc_dointvec (data=,conv=, ppos=, lenp=,buffer=, write=, table=)at kernel/sysctl.c:9642 proc_dointvec_minmax (ppos=, lenp=,buffer=, write=, table=)at kernel/sysctl.c:9643 proc_do_static_key (table=, write=1, buffer=0x0,lenp=0x0, ppos=0x7bf897061f9a0800) at kernel/sysctl.c:16434 0xffffffe000206792 in ftrace_make_call (rec=,addr=) at arch/riscv/kernel/ftrace.c:1095 0xffffffe0002c9c04 in __ftrace_replace_code(rec=0xffffffe01ae40c30, enable=3) at kernel/trace/ftrace.c:25036 0xffffffe0002ca0b2 in ftrace_replace_code (mod_flags=) at kernel/trace/ftrace.c:25307 0xffffffe0002ca26a in ftrace_modify_all_code (command=5) atkernel/trace/ftrace.c:26778 0xffffffe0002ca30e in __ftrace_modify_code (data=)at kernel/trace/ftrace.c:27039 0xffffffe0002c13b0 in multi_cpu_stop (data=0x0) at kernel/stop_machine.c:22410 0xffffffe0002c0fde in cpu_stopper_thread (cpu=) atkernel/stop_machine.c:49111 0xffffffe0002343de in smpboot_thread_fn (data=0x0) at kernel/smpboot.c:16512 0xffffffe00022f8b4 in kthread (_create=0xffffffe01af0c040) atkernel/kthread.c:29213 0xffffffe000201fac in handle_exception () at arch/riscv/kernel/entry.S:236 0xffffffe00020678a <+114>: auipc ra,0xffffe 0xffffffe00020678e <+118>: jalr -118(ra) # 0xffffffe000204714 0xffffffe000206792 <+122>: snez a0,a0(gdb) disassemble patch_text_nosyncDump of assembler code for function patch_text_nosync: 0xffffffe000204714 <+0>: addi sp,sp,-32 0xffffffe000204716 <+2>: sd s0,16(sp) 0xffffffe000204718 <+4>: sd ra,24(sp) 0xffffffe00020471a <+6>: addi s0,sp,32 0xffffffe00020471c <+8>: auipc ra,0x0 0xffffffe000204720 <+12>: jalr -384(ra) # 0xffffffe00020459c 0xffffffe000204724 <+16>: beqz a0,0xffffffe00020472e 0xffffffe000204726 <+18>: ld ra,24(sp) 0xffffffe000204728 <+20>: ld s0,16(sp) 0xffffffe00020472a <+22>: addi sp,sp,32 0xffffffe00020472c <+24>: ret 0xffffffe00020472e <+26>: sd a0,-24(s0) 0xffffffe000204732 <+30>: auipc ra,0x4 0xffffffe000204736 <+34>: jalr -1464(ra) # 0xffffffe00020817a 0xffffffe00020473a <+38>: ld a0,-24(s0) 0xffffffe00020473e <+42>: ld ra,24(sp) 0xffffffe000204740 <+44>: ld s0,16(sp) 0xffffffe000204742 <+46>: addi sp,sp,32 0xffffffe000204744 <+48>: ret(gdb) disassemble flush_icache_all-4Dump of assembler code for function flush_icache_all: 0xffffffe00020817a <+0>: addi sp,sp,-8 0xffffffe00020817c <+2>: sd ra,0(sp) 0xffffffe00020817e <+4>: auipc ra,0xfffff 0xffffffe000208182 <+8>: jalr -1822(ra) # 0xffffffe000206a60 0xffffffe000208186 <+12>: ld ra,0(sp) 0xffffffe000208188 <+14>: addi sp,sp,8 0xffffffe00020818a <+0>: addi sp,sp,-16 0xffffffe00020818c <+2>: sd s0,0(sp) 0xffffffe00020818e <+4>: sd ra,8(sp) 0xffffffe000208190 <+6>: addi s0,sp,16 0xffffffe000208192 <+8>: li a0,0 0xffffffe000208194 <+10>: auipc ra,0xfffff 0xffffffe000208198 <+14>: jalr -410(ra) # 0xffffffe000206ffa 0xffffffe00020819c <+18>: ld s0,0(sp) 0xffffffe00020819e <+20>: ld ra,8(sp) 0xffffffe0002081a0 <+22>: addi sp,sp,16 0xffffffe0002081a2 <+24>: ret(gdb) frame 5(rec=0xffffffe01ae40c30, enable=3) at kernel/trace/ftrace.c:25032503 return ftrace_make_call(rec, ftrace_addr);(gdb) p /x rec->ip$2 = 0xffffffe00020817a -> flush_icache_all !When we modified flush_icache_all's patchable-entry with ftrace_caller: - Insert ftrace_caller at flush_icache_all prologue. - Call flush_icache_all to sync I/Dcache, but flush_icache_all isjust we modified by half.Link: https://lore.kernel.org/linux-riscv/CAJF2gTT=oDWesWe0JVWvTpGi60-gpbNhYLdFWN_5EbyeqoEDdw@mail.gmail.com/T/#tSigned-off-by: Guo Ren Reviewed-by: Atish Patra Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

67d94577 - riscv: Fixup wrong ftrace remove cflag

Thu, 17 Dec 2020 16:01:39 +0000

riscv: Fixup wrong ftrace remove cflagWe must use $(CC_FLAGS_FTRACE) instead of directly using -pg. Itwill cause -fpatchable-function-entry error.Signed-off-by: Guo Ren Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

20d38f7c - riscv: Allow building with kcov coverage

Fri, 26 Jun 2020 12:40:56 +0000

riscv: Allow building with kcov coverageAdd ARCH_HAS_KCOV and HAVE_GCC_PLUGINS to the riscv Kconfig.Also disable instrumentation of some early boot code and vdso.Boot-tested on QEMU's riscv64 virt machine.Signed-off-by: Tobias Klauser Acked-by: Dmitry Vyukov Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

59c4da86 - riscv: Add support to dump the kernel page tables

Thu, 12 Mar 2020 02:58:35 +0000

riscv: Add support to dump the kernel page tablesIn a similar manner to arm64, x86, powerpc, etc., it can traverse allpage tables, and dump the page table layout with the memory types andpermissions.Add a debugfs file at /sys/kernel/debug/kernel_page_tables to exportthe page table layout to userspace.Signed-off-by: Zong Li Tested-by: Alexandre Ghiti Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

d3ab332a - riscv: add ARCH_HAS_SET_MEMORY support

Mon, 09 Mar 2020 16:55:36 +0000

riscv: add ARCH_HAS_SET_MEMORY supportAdd set_memory_ro/rw/x/nx architecture hooks to change the pageattribution.Use own set_memory.h rather than generic set_memory.h(i.e. include/asm-generic/set_memory.h), because we want to add otherfunction prototypes here.Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

6435f773 - riscv: mm: add support for CONFIG_DEBUG_VIRTUAL

Thu, 02 Jan 2020 03:12:39 +0000

riscv: mm: add support for CONFIG_DEBUG_VIRTUALThis patch implements CONFIG_DEBUG_VIRTUAL to do additional checks onvirt_to_phys and __pa_symbol calls. virt_to_phys used for linear mappingcheck, and __pa_symbol used for kernel symbol check. In current RISC-V,kernel image maps to linear mapping area. If CONFIG_DEBUG_VIRTUAL isdisable, these two functions calculate the offset on the address fededdirectly without any checks.The result of test_debug_virtual as follows:[ 0.358456] ------------[ cut here ]------------[ 0.358738] virt_to_phys used for non-linear address: (____ptrval____) (0xffffffd000000000)[ 0.359174] WARNING: CPU: 0 PID: 1 at arch/riscv/mm/physaddr.c:16 __virt_to_phys+0x3c/0x50[ 0.359409] Modules linked in:[ 0.359630] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc3-00002-g5133c5c0ca13 #57[ 0.359861] epc: ffffffe000253d1a ra : ffffffe000253d1a sp : ffffffe03aa87da0[ 0.360019] gp : ffffffe000ae03b0 tp : ffffffe03aa88000 t0 : ffffffe000af2660[ 0.360175] t1 : 0000000000000064 t2 : 00000000000000b7 s0 : ffffffe03aa87dc0[ 0.360330] s1 : ffffffd000000000 a0 : 000000000000004f a1 : 0000000000000000[ 0.360492] a2 : 0000000000000000 a3 : 0000000000000000 a4 : ffffffe000a84358[ 0.360672] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000[ 0.360876] s2 : ffffffe000ae0600 s3 : ffffffe00000fc7c s4 : ffffffe0000224b0[ 0.361067] s5 : ffffffe000030890 s6 : ffffffe000022470 s7 : 0000000000000008[ 0.361267] s8 : ffffffe0000002c4 s9 : ffffffe000ae0640 s10: ffffffe000ae0630[ 0.361453] s11: 0000000000000000 t3 : 0000000000000000 t4 : 000000000001e6d0[ 0.361636] t5 : ffffffe000ae0a18 t6 : ffffffe000aee54e[ 0.361806] status: 0000000000000120 badaddr: 0000000000000000 cause: 0000000000000003[ 0.362056] ---[ end trace aec0bf78d4978122 ]---[ 0.362404] PA: 0xfffffff080200000 for VA: 0xffffffd000000000[ 0.362607] PA: 0x00000000baddd2d0 for VA: 0xffffffe03abdd2d0Signed-off-by: Zong Li Reviewed-by: Paul Walmsley Tested-by: Paul Walmsley Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

8ad8b727 - riscv: Add KASAN support

Mon, 06 Jan 2020 18:38:32 +0000

riscv: Add KASAN supportThis patch ports the feature Kernel Address SANitizer (KASAN).Note: The start address of shadow memory is at the beginning of kernelspace, which is 2^64 - (2^39 / 2) in SV39. The size of the kernel space is2^38 bytes so the size of shadow memory should be 2^38 / 8. Thus, theshadow memory would not overlap with the fixmap area.There are currently two limitations in this port,1. RV64 only: KASAN need large address space for extra shadow memoryregion.2. KASAN can't debug the modules since the modules are allocated in VMALLOCarea. We mapped the shadow memory, which corresponding to VMALLOC area, tothe kasan_early_shadow_page because we don't have enough physical space forall the shadow memory corresponding to VMALLOC area.Signed-off-by: Nick Hu Reported-by: Greentime Hu Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/mm/Makefile

9209fb51 - riscv: move sifive_l2_cache.c to drivers/soc

Thu, 07 Nov 2019 09:20:39 +0000

riscv: move sifive_l2_cache.c to drivers/socThe sifive_l2_cache.c is in no way related to RISC-V architecturememory management. It is a little stub driver working around the factthat the EDAC maintainers prefer their drivers to be structured in acertain way that doesn't fit the SiFive SOCs.Move the file to drivers/soc and add a Kconfig option for it, as wellas the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")Signed-off-by: Christoph Hellwig Reviewed-by: Borislav Petkov [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]Signed-off-by: Paul Walmsley List of files: /linux-6.15/arch/riscv/mm/Makefile

6bd33e1e - riscv: add nommu support

Mon, 28 Oct 2019 12:10:41 +0000

riscv: add nommu supportThe kernel runs in M-mode without using page tables, and thus can't runbare metal without help from additional firmware.Most of the patch is just stubbing out code not needed without pagetables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack.In addition to enabling the nommu code a new defconfig for a smallkernel image that can run in nommu mode on qemu is also provided, to runa kernel in qemu you can use the following command line:qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0Contains contributions from Damien Le Moal .Signed-off-by: Christoph Hellwig Reviewed-by: Anup Patel [paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards around PCI_IOBASE definition to fix build issues; fixed checkpatch issues; move the PCI_IO_* and VMEMMAP address space macros along with the others; resolve sparse warning]Signed-off-by: Paul Walmsley List of files: /linux-6.15/arch/riscv/mm/Makefile

38af5782 - riscv: use the generic ioremap code

Tue, 13 Aug 2019 09:27:56 +0000

riscv: use the generic ioremap codeUse the generic ioremap code instead of providing a local version.Note that this relies on the asm-generic no-op definition ofpgprot_noncached.Signed-off-by: Christoph Hellwig Reviewed-by: Paul Walmsley Tested-by: Paul Walmsley # rv32, rv64 bootAcked-by: Paul Walmsley # arch/riscv List of files: /linux-6.15/arch/riscv/mm/Makefile