Changes in Makefile

a79be02b - Fix mis-uses of 'cc-option' for warning disablement

Wed, 23 Apr 2025 17:08:29 +0000

Fix mis-uses of 'cc-option' for warning disablementThis was triggered by one of my mis-uses causing odd build warnings onsparc in linux-next, but while figuring out why the "obviously correct"use of cc-option caused such odd breakage, I found eight other cases ofthe same thing in the tree.The root cause is that 'cc-option' doesn't work for checking negativewarning options (ie things like '-Wno-stringop-overflow') because gccwill silently accept options it doesn't recognize, and so 'cc-option'ends up thinking they are perfectly fine.And it all works, until you have a situation where _another_ warning isemitted. At that point the compiler will go "Hmm, maybe the userintended to disable this warning but used that wrong option that Ididn't recognize", and generate a warning for the unrecognized negativeoption.Which explains why we have several cases of this in the tree: the'cc-option' test really doesn't work for this situation, but most of thetime it simply doesn't matter that ity doesn't work.The reason my recently added case caused problems on sparc was pointedout by Thomas Weißschuh: the sparc build had a previous explicit warningthat then triggered the new one.I think the best fix for this would be to make 'cc-option' a bit smarterabout this sitation, possibly by adding an intentional warning to thetest case that then triggers the unrecognized option warning reliably.But the short-term fix is to replace 'cc-option' with an existing helperdesigned for this exact case: 'cc-disable-warning', which picks thenegative warning but uses the positive form for testing the compilersupport.Reported-by: Stephen Rothwell Link: https://lore.kernel.org/all/20250422204718.0b4e3f81@canb.auug.org.au/Explained-by: Thomas Weißschuh Signed-off-by: Linus Torvalds List of files: /linux-6.15/arch/riscv/kernel/Makefile

4bf97069 - riscv: Add ghostwrite vulnerability

Thu, 14 Nov 2024 02:21:20 +0000

riscv: Add ghostwrite vulnerabilityFollow the patterns of the other architectures that useGENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwritevulnerability and mitigation. The mitigation is to disable all vectorwhich is accomplished by clearing the bit from the cpufeature field.Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, sothe vulerability will only be mitigated on these CPUs.Signed-off-by: Charlie Jenkins Tested-by: Yangyu Chen Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-14-236c22791ef9@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

afedc312 - riscv: Do not use fortify in early code

Wed, 09 Oct 2024 07:27:49 +0000

riscv: Do not use fortify in early codeEarly code designates the code executed when the MMU is not yet enabled,and this comes with some limitations (seeDocumentation/arch/riscv/boot.rst, section "Pre-MMU execution").FORTIFY_SOURCE must be disabled then since it can trigger kernel panicsas reported in [1].Reported-by: Jason Montleon Closes: https://lore.kernel.org/linux-riscv/CAJD_bPJes4QhmXY5f63GHV9B9HFkSCoaZjk-qCT2NGS7Q9HODg@mail.gmail.com/ [1]Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")Fixes: 26e7aacb83df ("riscv: Allow to downgrade paging mode from the command line")Cc: stable@vger.kernel.orgSigned-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20241009072749.45006-1-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

e7c9d66e - RISC-V: Report vector unaligned access speed hwprobe

Thu, 17 Oct 2024 19:00:22 +0000

RISC-V: Report vector unaligned access speed hwprobeDetect if vector misaligned accesses are faster or slower thanequivalent vector byte accesses. This is useful for usermode to knowwhether vector byte accesses or vector misaligned accesses have a betterbandwidth for operations like memcpy.Signed-off-by: Jesse Taube Reviewed-by: Charlie Jenkins Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-5-5b33500160f8@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

d1703dc7 - RISC-V: Detect unaligned vector accesses supported

Thu, 17 Oct 2024 19:00:21 +0000

RISC-V: Detect unaligned vector accesses supportedRun an unaligned vector access to test if the system supportsvector unaligned access. Add the result to a new key in hwprobe.This is useful for usermode to know if vector misaligned accesses aresupported and if they are faster or slower than equivalent byte accesses.Signed-off-by: Jesse Taube Signed-off-by: Charlie Jenkins Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-4-5b33500160f8@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

c05a62c9 - RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED

Thu, 17 Oct 2024 19:00:20 +0000

RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNEDReplace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED to allowfor the addition of RISCV_VECTOR_MISALIGNED in a later patch.Signed-off-by: Jesse Taube Reviewed-by: Conor Dooley Reviewed-by: Charlie Jenkins Reviewed-by: Evan Green Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-3-5b33500160f8@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

1ff95eb2 - riscv: Fix RISCV_ALTERNATIVE_EARLY

Thu, 29 Aug 2024 16:50:48 +0000

riscv: Fix RISCV_ALTERNATIVE_EARLYRISCV_ALTERNATIVE_EARLY will issue sbi_ecall() very early in the bootprocess, before the first memory mapping is setup so we can't have anyinstrumentation happening here.In addition, when the kernel is relocatable, we must also not issue anyrelocation this early since they would have been patched virtually only.So, instead of disabling instrumentation for the whole kernel/sbi.c fileand compiling it with -fno-pie, simply move __sbi_ecall() and__sbi_base_ecall() into their own file where this is fixed.Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240813-pony-truck-3e7a83e9759e@spud/Reported-by: syzbot+cfbcb82adf6d7279fd35@syzkaller.appspotmail.comCloses: https://lore.kernel.org/linux-riscv/00000000000065062c061fcec37b@google.com/Fixes: 1745cfafebdf ("riscv: don't use global static vars to store alternative data")Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20240829165048.49756-1-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

23c996fc - riscv: Extend cpufeature.c to detect vendor extensions

Fri, 19 Jul 2024 16:15:18 +0000

riscv: Extend cpufeature.c to detect vendor extensionsInstead of grouping all vendor extensions into the same riscv_isa_extthat standard instructions use, create a struct"riscv_isa_vendor_ext_data_list" that allows each vendor to maintaintheir vendor extensions independently of the standard extensions.xandespmu is currently the only vendor extension so that is the onlyextension that is affected by this change.An additional benefit of this is that the extensions of each vendor canbe conditionally enabled. A config RISCV_ISA_VENDOR_EXT_ANDES has beenadded to allow for that.Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu Tested-by: Yu Chien Peter Lin Reviewed-by: Yu Chien Peter Lin Link: https://lore.kernel.org/r/20240719-support_vendor_extensions-v3-1-0af7587bbec0@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

eabd9db6 - ACPI: RISCV: Add NUMA support based on SRAT and SLIT

Thu, 13 Jun 2024 08:54:33 +0000

ACPI: RISCV: Add NUMA support based on SRAT and SLITAdd acpi_numa.c file to enable parse NUMA information fromACPI SRAT and SLIT tables. SRAT table provide CPUs(Hart) andmemory nodes to proximity domain mapping, while SLIT tableprovide the distance metrics between proximity domains.Signed-off-by: Haibo Xu Reviewed-by: Sunil V L Reviewed-by: Hanjun Guo Link: https://lore.kernel.org/r/65dbad1fda08a32922c44886e4581e49b4a2fecc.1718268003.git.haibo1.xu@intel.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

77acc6b5 - riscv: add support for kernel-mode FPU

Fri, 29 Mar 2024 07:18:26 +0000

riscv: add support for kernel-mode FPUThis is motivated by the amdgpu DRM driver, which needs floating-pointcode to support recent hardware. That code is not performance-critical,so only provide a minimal non-preemptible implementation for now.Support is limited to riscv64 because riscv32 requires runtime (libgcc)assistance to convert between doubles and 64-bit integers.Link: https://lkml.kernel.org/r/20240329072441.591471-12-samuel.holland@sifive.comSigned-off-by: Samuel Holland Acked-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Reviewed-by: Christoph Hellwig Acked-by: Christian König Cc: Alex Deucher Cc: Borislav Petkov (AMD) Cc: Catalin Marinas Cc: Dave Hansen Cc: Huacai Chen Cc: Ingo Molnar Cc: Jonathan Corbet Cc: Masahiro Yamada Cc: Michael Ellerman Cc: Nathan Chancellor Cc: Nicolas Schier Cc: Russell King Cc: Thomas Gleixner Cc: WANG Xuerui Cc: Will Deacon Signed-off-by: Andrew Morton List of files: /linux-6.15/arch/riscv/kernel/Makefile

f413aae9 - riscv: Set unaligned access speed at compile time

Fri, 08 Mar 2024 18:25:58 +0000

riscv: Set unaligned access speed at compile timeIntroduce Kconfig options to set the kernel unaligned access support.These options provide a non-portable alternative to the runtimeunaligned access probe.To support this, the unaligned access probing code is moved into it'sown file and gated behind a new RISCV_PROBE_UNALIGNED_ACCESS_SUPPORToption.Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Tested-by: Samuel Holland Link: https://lore.kernel.org/r/20240308-disable_misaligned_probe_config-v9-4-a388770ba0ce@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

443cbaf9 - crash: split vmcoreinfo exporting code out from crash_core.c

Wed, 24 Jan 2024 05:12:42 +0000

crash: split vmcoreinfo exporting code out from crash_core.cNow move the relevant codes into separate files:kernel/crash_reserve.c, include/linux/crash_reserve.h.And add config item CRASH_RESERVE to control its enabling.And also update the old ifdeffery of CONFIG_CRASH_CORE, including of and config item dependency on CRASH_COREaccordingly.And also do renaming as follows: - arch/xxx/kernel/{crash_core.c => vmcore_info.c}because they are only related to vmcoreinfo exporting on x86, arm64,riscv.And also Remove config item CRASH_CORE, and rely on CONFIG_KEXEC_CORE todecide if build in crash_core.c.[yang.lee@linux.alibaba.com: remove duplicated include in vmcore_info.c] Link: https://lkml.kernel.org/r/20240126005744.16561-1-yang.lee@linux.alibaba.comLink: https://lkml.kernel.org/r/20240124051254.67105-3-bhe@redhat.comSigned-off-by: Baoquan He Signed-off-by: Yang Li Acked-by: Hari Bathini Cc: Al Viro Cc: Eric W. Biederman Cc: Pingfan Liu Cc: Klara Modin Cc: Michael Kelley Cc: Nathan Chancellor Cc: Stephen Rothwell Cc: Yang Li Signed-off-by: Andrew Morton List of files: /linux-6.15/arch/riscv/kernel/Makefile

68034138 - riscv: add CALLER_ADDRx support

Fri, 02 Feb 2024 01:51:02 +0000

riscv: add CALLER_ADDRx supportCALLER_ADDRx returns caller's address at specified level, they are usedfor several tracers. These macros eventually use__builtin_return_address(n) to get the caller's address if arch doesn'tdefine their own implementation.In RISC-V, __builtin_return_address(n) only works when n == 0, we needto walk the stack frame to get the caller's address at specified level.data.level started from 'level + 3' due to the call flow of gettingcaller's address in RISC-V implementation. If we don't have additionalthree iteration, the level is corresponding to follows:callsite -> return_address -> arch_stack_walk -> walk_stackframe| | | |level 3 level 2 level 1 level 0Fixes: 10626c32e382 ("riscv/ftrace: Add basic support")Cc: stable@vger.kernel.orgReviewed-by: Alexandre Ghiti Signed-off-by: Zong Li Link: https://lore.kernel.org/r/20240202015102.26251-1-zong.li@sifive.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

ecd2ada8 - riscv: Add support for kernel mode vector

Mon, 15 Jan 2024 05:59:20 +0000

riscv: Add support for kernel mode vectorAdd kernel_vector_begin() and kernel_vector_end() function declarationsand corresponding definitions in kernel_mode_vector.cThese are needed to wrap uses of vector in kernel mode.Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Eric Biggers Tested-by: Björn Töpel Tested-by: Lad Prabhakar Link: https://lore.kernel.org/r/20240115055929.4736-2-andy.chiu@sifive.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

53b2b228 - RISC-V: Move the hwprobe syscall to its own file

Wed, 22 Nov 2023 16:47:03 +0000

RISC-V: Move the hwprobe syscall to its own fileAs Palmer says, hwprobe is "sort of its own thing now, and it's onlygoing to get bigger..."Suggested-by: Palmer Dabbelt Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20231122164700.127954-8-ajones@ventanamicro.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

323925ed - RISC-V: paravirt: Add skeleton for pv-time support

Wed, 20 Dec 2023 16:00:14 +0000

RISC-V: paravirt: Add skeleton for pv-time supportAdd the files and functions needed to support paravirt time onRISC-V. Also include the common code needed for the firstapplication of pv-time, which is steal-time. In the nextpatches we'll complete the functions to fully enable steal-timesupport.Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Atish Patra Signed-off-by: Andrew Jones Signed-off-by: Anup Patel List of files: /linux-6.15/arch/riscv/kernel/Makefile

d53a154c - riscv, kexec: fix the ifdeffery for AFLAGS_kexec_relocate.o

Fri, 01 Dec 2023 06:25:38 +0000

riscv, kexec: fix the ifdeffery for AFLAGS_kexec_relocate.oThis was introduced in commit fba8a8674f68 ("RISC-V: Add kexecsupport").It should work on CONFIG_KEXEC_CORE, but not CONFIG_KEXEC only, sincewe could set CONFIG_KEXEC_FILE=y and CONFIG_KEXEC=N, or only setCONFIG_CRASH_DUMP=y and disable both CONFIG_KEXEC and CONFIG_KEXEC_FILE.In these cases, the AFLAGS won't take effect with the current ifdefferyfor AFLAGS_kexec_relocate.o.So fix it now.Link: https://lkml.kernel.org/r/20231201062538.27240-1-bhe@redhat.comSigned-off-by: Baoquan He Cc: Albert Ou Cc: Changbin Du Cc: Nick Kossifidis Cc: Palmer Dabbelt Cc: Paul Walmsley Signed-off-by: Andrew Morton List of files: /linux-6.15/arch/riscv/kernel/Makefile

af71bc19 - riscv: Add tests for riscv module loading

Wed, 01 Nov 2023 18:33:01 +0000

riscv: Add tests for riscv module loadingAdd test cases for the two main groups of relocations added: SUB andSET, along with uleb128.Signed-off-by: Charlie Jenkins Link: https://lore.kernel.org/r/20231101-module_relocations-v9-3-8dfa3483c400@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

7c832321 - riscv: add support for misaligned trap handling in S-mode

Wed, 04 Oct 2023 15:13:59 +0000

riscv: add support for misaligned trap handling in S-modeMisalignment trap handling is only supported for M-mode and uses directaccesses to user memory. In S-mode, when handling usermode fault, thisrequires to use the get_user()/put_user() accessors. Implementload_u8(), store_u8() and get_insn() using these accessors foruserspace and direct text access for kernel.Signed-off-by: Clément Léger Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20231004151405.521596-3-cleger@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile

584ea656 - RISC-V: Probe for unaligned access speed

Fri, 18 Aug 2023 19:41:35 +0000

RISC-V: Probe for unaligned access speedRather than deferring unaligned access speed determinations to a vendorfunction, let's probe them and find out how fast they are. If wedetermine that an unaligned word access is faster than N byte accesses,mark the hardware's unaligned access as "fast". Otherwise, we markaccesses as slow.The algorithm itself runs for a fixed amount of jiffies. Within eachiteration it attempts to time a single loop, and then keeps only the best(fastest) loop it saw. This algorithm was found to have lower variance fromrun to run than my first attempt, which counted the total number ofiterations that could be done in that fixed amount of jiffies. By takingonly the best iteration in the loop, assuming at least one loop wasn'tperturbed by an interrupt, we eliminate the effects of interrupts andother "warm up" factors like branch prediction. The only downside is itdepends on having an rdtime granular and accurate enough to measure asingle copy. If we ever manage to complete a loop in 0 rdtime ticks, weleave the unaligned setting at UNKNOWN.There is a slight change in user-visible behavior here. Previously, allboards except the THead C906 reported misaligned access speed ofUNKNOWN. C906 reported FAST. With this change, since we're now measuringmisaligned access speed on each hart, all RISC-V systems will have thiskey set as either FAST or SLOW.Currently, we don't have a way to confidently measure the difference betweenSLOW and EMULATED, so we label anything not fast as SLOW. This willmislabel some systems that are actually EMULATED as SLOW. When we getsupport for delegating misaligned access traps to the kernel (as opposedto the firmware quietly handling it), we can explicitly test in Linux tosee if unaligned accesses trap. Those systems will start to reportEMULATED, though older (today's) systems without that new SBI mechanismwill continue to report SLOW.I've updated the documentation for those hwprobe values to reflectthis, specifically: SLOW may or may not be emulated by software, and FASTrepresents means being faster than equivalent byte accesses. The changein documentation is accurate with respect to both the former and currentbehavior.Signed-off-by: Evan Green Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230818194136.4084400-2-evan@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/kernel/Makefile