<?xml version="1.0"?>
<?xml-stylesheet type="text/xsl" href="/rss.xsl.xml"?>
<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/">
<channel>
    <title>Changes in Makefile</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>b75db25c - riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/arch/riscv/errata/sifive/Makefile#b75db25c</link>
        <description>riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledThe errata_cip_453.o should be built only when the KconfigCONFIG_ERRATA_SIFIVE_CIP_453 is enabled.Reported-by: kernel test robot &lt;lkp@intel.com&gt;Signed-off-by: Vincent &lt;vincent.chen@sifive.com&gt;Fixes: 0e0d4992517f (&quot;riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y&quot;)Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;

            List of files:
            /linux-6.15/arch/riscv/errata/sifive/Makefile</description>
        <pubDate>Fri, 21 May 2021 23:40:15 +0000</pubDate>
        <dc:creator>Vincent &lt;vincent.chen@sifive.com&gt;</dc:creator>
    </item>
<item>
        <title>800149a7 - riscv: sifive: Apply errata &quot;cip-453&quot; patch</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/arch/riscv/errata/sifive/Makefile#800149a7</link>
        <description>riscv: sifive: Apply errata &quot;cip-453&quot; patchAdd sign extension to the $badaddr before addressing the instruction pagefault and instruction access fault to workaround the issue &quot;cip-453&quot;.To avoid affecting the existing code sequence, this patch will creates twotrampolines to add sign extension to the $badaddr. By the &quot;alternative&quot;mechanism, these two trampolines will replace the original exceptionhandler of instruction page fault and instruction access fault in theexcp_vect_table. In this case, only the specific SiFive CPU core jumps tothe do_page_fault and do_trap_insn_fault through these two trampolines.Other CPUs are not affected.Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;

            List of files:
            /linux-6.15/arch/riscv/errata/sifive/Makefile</description>
        <pubDate>Mon, 22 Mar 2021 14:26:05 +0000</pubDate>
        <dc:creator>Vincent Chen &lt;vincent.chen@sifive.com&gt;</dc:creator>
    </item>
<item>
        <title>1a0e5dbd - riscv: sifive: Add SiFive alternative ports</title>
        <link>http://172.16.0.5:8080/history/linux-6.15/arch/riscv/errata/sifive/Makefile#1a0e5dbd</link>
        <description>riscv: sifive: Add SiFive alternative portsAdd required ports of the Alternative scheme for SiFive.Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;

            List of files:
            /linux-6.15/arch/riscv/errata/sifive/Makefile</description>
        <pubDate>Mon, 22 Mar 2021 14:26:04 +0000</pubDate>
        <dc:creator>Vincent Chen &lt;vincent.chen@sifive.com&gt;</dc:creator>
    </item>
</channel>
</rss>
