Changes in Makefile

bb58e157 - RISC-V: errata: Use medany for relocatable builds

Wed, 26 Mar 2025 22:45:07 +0000

RISC-V: errata: Use medany for relocatable buildsWe're trying to mix non-PIC/PIE objects into the otherwise-PIErelocatable kernels, to avoid GOT/PLT references during early bootalternative resolution (which happens before the GOT/PLT are set up).riscv64-unknown-linux-gnu-ld: arch/riscv/errata/sifive/errata.o: relocation R_RISCV_HI20 against `tlb_flush_all_threshold' can not be used when making a shared object; recompile with -fPICriscv64-unknown-linux-gnu-ld: arch/riscv/errata/thead/errata.o: relocation R_RISCV_HI20 against `riscv_cbom_block_size' can not be used when making a shared object; recompile with -fPICFixes: 8dc2a7e8027f ("riscv: Fix relocatable kernels with early alternatives using -fno-pie")Link: https://lore.kernel.org/r/20250326224506.27165-2-palmer@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

afedc312 - riscv: Do not use fortify in early code

Wed, 09 Oct 2024 07:27:49 +0000

riscv: Do not use fortify in early codeEarly code designates the code executed when the MMU is not yet enabled,and this comes with some limitations (seeDocumentation/arch/riscv/boot.rst, section "Pre-MMU execution").FORTIFY_SOURCE must be disabled then since it can trigger kernel panicsas reported in [1].Reported-by: Jason Montleon Closes: https://lore.kernel.org/linux-riscv/CAJD_bPJes4QhmXY5f63GHV9B9HFkSCoaZjk-qCT2NGS7Q9HODg@mail.gmail.com/ [1]Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")Fixes: 26e7aacb83df ("riscv: Allow to downgrade paging mode from the command line")Cc: stable@vger.kernel.orgSigned-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20241009072749.45006-1-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

e021ae7f - riscv: errata: Add Andes alternative ports

Fri, 18 Aug 2023 13:57:19 +0000

riscv: errata: Add Andes alternative portsAdd required ports of the Alternative scheme for Andes CPU cores.I/O Coherence Port (IOCP) provides an AXI interface for connecting externalnon-caching masters, such as DMA controllers. IOCP is a specificationoption and is disabled on the Renesas RZ/Five SoC due to this reason cachemanagement needs a software workaround.Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1Link: https://lore.kernel.org/r/20230818135723.80612-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

8dc2a7e8 - riscv: Fix relocatable kernels with early alternatives using -fno-pie

Fri, 26 May 2023 15:46:30 +0000

riscv: Fix relocatable kernels with early alternatives using -fno-pieEarly alternatives are called with the mmu disabled, and then should notaccess any global symbols through the GOT since it requires relocations,relocations that we do before but *virtually*. So only use medany codemodel for this early code.Signed-off-by: Alexandre Ghiti Tested-by: Conor Dooley # booted on nezha & unmatchedFixes: 39b33072941f ("riscv: Introduce CONFIG_RELOCATABLE")Link: https://lore.kernel.org/r/20230526154630.289374-1-alexghiti@rivosinc.comSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

a35707c3 - riscv: add memory-type errata for T-Head

Wed, 11 May 2022 19:29:21 +0000

riscv: add memory-type errata for T-HeadSome current cpus based on T-Head cores implement memory-typesway different than described in the svpbmt spec even goingso far as using PTE bits marked as reserved.Add the T-Head vendor-id and necessary errata code toreplace the affected instructions.Signed-off-by: Heiko Stuebner Tested-by: Samuel Holland Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.deSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

e64f737a - riscv: integrate alternatives better into the main architecture

Wed, 11 May 2022 19:29:10 +0000

riscv: integrate alternatives better into the main architectureRight now the alternatives need to be explicitly enabled anderratas are limited to SiFive ones.We want to use alternatives not only for patching soc erratas,but in the future also for handling different behaviour dependingon the existence of future extensions.So move the core alternatives over to the kernel subdirectoryand move the CONFIG_RISCV_ALTERNATIVE to be a hidden symbolwhich we expect relevant erratas and extensions to just selectif needed.Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich Link: https://lore.kernel.org/r/20220511192921.2223629-2-heiko@sntech.deSigned-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

1a0e5dbd - riscv: sifive: Add SiFive alternative ports

Mon, 22 Mar 2021 14:26:04 +0000

riscv: sifive: Add SiFive alternative portsAdd required ports of the Alternative scheme for SiFive.Signed-off-by: Vincent Chen Reviewed-by: Anup Patel Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile

6f4eea90 - riscv: Introduce alternative mechanism to apply errata solution

Mon, 22 Mar 2021 14:26:03 +0000

riscv: Introduce alternative mechanism to apply errata solutionIntroduce the "alternative" mechanism from ARM64 and x86 to apply the CPUvendors' errata solution at runtime. The main purpose of this patch isto provide a framework. Therefore, the implementation is quite basic fornow so that some scenarios could not use this schemei, such as patchingcode to a module, relocating the patching code and heterogeneous CPUtopology.Users could use the macro ALTERNATIVE to apply an errata to the existingcode flow. In the macro ALTERNATIVE, users need to specify the manufacturerinformation(vendorid, archid, and impid) for this errata. Therefore, kernelwill know this errata is suitable for which CPU core. During the bootingprocedure, kernel will select the errata required by the CPU core and thenpatch it. It means that the kernel only applies the errata to the specifiedCPU core. In this case, the vendor's errata does not affect each other atruntime. The above patching procedure only occurs during the booting phase,so we only take the overhead of the "alternative" mechanism once.This "alternative" mechanism is enabled by default to ensure that allrequired errata will be applied. However, users can disable this feature bythe Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE".Signed-off-by: Vincent Chen Reviewed-by: Anup Patel Signed-off-by: Palmer Dabbelt List of files: /linux-6.15/arch/riscv/errata/Makefile