Changes in csum_partial.S

9259e15b - mips: replace #include with #include

Mon, 07 Aug 2023 15:32:42 +0000

mips: replace #include with #include Commit ddb5cdbafaaa ("kbuild: generate KSYMTAB entries by modpost")deprecated , which is now a wrapper of .Replace #include with #include .After all the lines are converted, and will be removed.Signed-off-by: Masahiro Yamada Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer List of files: /linux-6.15/arch/mips/lib/csum_partial.S

fa62f39d - MIPS: Fix build error due to PTR used in more places

Tue, 25 Jan 2022 14:19:44 +0000

MIPS: Fix build error due to PTR used in more placesUse PTR_WD instead of PTR to avoid clashes with other parts.Signed-off-by: Thomas Bogendoerfer List of files: /linux-6.15/arch/mips/lib/csum_partial.S

1cd95ab8 - mips: propagate the calling convention change down into __csum_partial_copy_..._user()

Sun, 19 Jul 2020 21:37:15 +0000

mips: propagate the calling convention change down into __csum_partial_copy_..._user()and turn the exception handlers into simply returning 0, whichsimplifies the hell out of things in csum_partial.SSigned-off-by: Al Viro List of files: /linux-6.15/arch/mips/lib/csum_partial.S

f863c65c - mips: __csum_partial_copy_kernel() has no users left

Sun, 19 Jul 2020 18:01:58 +0000

mips: __csum_partial_copy_kernel() has no users leftSigned-off-by: Al Viro List of files: /linux-6.15/arch/mips/lib/csum_partial.S

cc44c17b - csum_partial_copy_nocheck(): drop the last argument

Sat, 11 Jul 2020 04:12:07 +0000

csum_partial_copy_nocheck(): drop the last argumentIt's always 0. Note that we theoretically could use ~0U as well -result will be the same modulo 0xffff, _if_ the damn thing did theright thing for any value of initial sum; later we'll make use ofthat when convenient.However, unlike csum_and_copy_..._user(), there are instances thatdid not work for arbitrary initial sums; c6x is one such.Signed-off-by: Al Viro List of files: /linux-6.15/arch/mips/lib/csum_partial.S

ab7c01fd - mips: Add MIPS Release 5 support

Thu, 21 May 2020 14:07:14 +0000

mips: Add MIPS Release 5 supportThere are five MIPS32/64 architecture releases currently available:from 1 to 6 except fourth one, which was intentionally skipped.Three of them can be called as major: 1st, 2nd and 6th, that not onlyhave some system level alterations, but also introduced significantcore/ISA level updates. The rest of the MIPS architecture releases areminor.Even though they don't have as much ISA/system/core level changesas the major ones with respect to the previous releases, they stillprovide a set of updates (I'd say they were intended to be theintermediate releases before a major one) that might be useful for thekernel and user-level code, when activated by the kernel or compiler.In particular the following features were introduced or ended up beingavailable at/after MIPS32/64 Release 5 architecture:+ the last release of the misaligned memory access instructions,+ virtualisation - VZ ASE - is optional component of the arch,+ SIMD - MSA ASE - is optional component of the arch,+ DSP ASE is optional component of the arch,+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers) must be available if FPU is implemented,+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits are available.+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without accidentally clearing LL-bit when returning from an interrupt, exception, or error trap,+ XPA feature together with extended versions of CPx registers is introduced, which needs to have mfhc0/mthc0 instructions available.So due to these changes GNU GCC provides an extended instructions setsupport for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Eventhough the architecture alteration isn't that big, it still worth to betaken into account by the kernel software. Finally we can't deny thatsome optimization/limitations might be found in future and implementedon some level in kernel or compiler. In this case having evenintermediate MIPS architecture releases support would be more thanuseful.So the most of the changes provided by this commit can be split intoeither compile- or runtime configs related. The compile-time relatedchanges are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5configs and concern the code activating MIPSR2 or MIPSR6 alreadyimplemented features (like eretnc/LLbit, mthc0/mfhc0). In additionCPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 basedplatforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changesconcerns the features which are handled with respect to the MIPS ISArevision detected at run-time by means of CP0.Config.{AT,AR} bits. Alasthese fields can be used to detect either r1 or r2 or r6 releases.But since we know which CPUs in fact support the R5 arch, we can manuallyset MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and thenuse cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.Since XPA/EVA provide too complex alterationss and to have them used withMIPS32 Release 2 charged kernels (for compatibility with current platformconfigs) they are left to be setup as a separate kernel configs.Co-developed-by: Alexey Malahov Signed-off-by: Alexey Malahov Signed-off-by: Serge Semin Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc: Rob Herring Cc: devicetree@vger.kernel.orgSigned-off-by: Thomas Bogendoerfer List of files: /linux-6.15/arch/mips/lib/csum_partial.S

268a2d60 - MIPS: Loongson64: Rename CPU TYPES

Sun, 20 Oct 2019 14:43:13 +0000

MIPS: Loongson64: Rename CPU TYPESCPU_LOONGSON2 -> CPU_LOONGSON2EFCPU_LOONGSON3 -> CPU_LOONGSON64As newer loongson-2 products (2G/2H/2K1000) can share kernelimplementation with loongson-3 while 2E/2F are less similar withother LOONGSON64 products.Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.orgCc: chenhc@lemote.comCc: paul.burton@mips.com List of files: /linux-6.15/arch/mips/lib/csum_partial.S

23130042 - MIPS: Export csum functions alongside their definitions

Mon, 07 Nov 2016 11:14:13 +0000

MIPS: Export csum functions alongside their definitionsNow that EXPORT_SYMBOL can be used from assembly source, move theEXPORT_SYMBOL invocations for the csum_partial_* functions to bealongside their definitions.Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.orgPatchwork: https://patchwork.linux-mips.org/patch/14512/Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

615eb603 - MIPS: csum_partial: Improve instruction parallelism.

Thu, 26 Mar 2015 17:07:24 +0000

MIPS: csum_partial: Improve instruction parallelism.Computing sum introduces true data dependency. This patch removes sometrue data depdendencies, hence increases instruction level parallelism.This patch brings up to 50% csum performance gain on Loongson 3a.One example about how this patch works is in CSUM_BIGCHUNK1:// ** original ** vs ** patch applied ** ADDC(sum, t0) ADDC(t0, t1) ADDC(sum, t1) ADDC(t2, t3) ADDC(sum, t2) ADDC(sum, t0) ADDC(sum, t3) ADDC(sum, t2)In the original implementation, each ADDC(sum, ...) depends on the sumvalue updated by previous ADDC(as source operand).With this patch applied, the first two ADDC operations are independent,hence can be executed simultaneously if possible.Another example is in the "copy and sum calculating chunk":// ** original ** vs ** patch applied ** STORE(t0, UNIT(0) ... STORE(t0, UNIT(0) ... ADDC(sum, t0) ADDC(t0, t1) STORE(t1, UNIT(1) ... STORE(t1, UNIT(1) ... ADDC(sum, t1) ADDC(sum, t0) STORE(t2, UNIT(2) ... STORE(t2, UNIT(2) ... ADDC(sum, t2) ADDC(t2, t3) STORE(t3, UNIT(3) ... STORE(t3, UNIT(3) ... ADDC(sum, t3) ADDC(sum, t2)With this patch applied, ADDC and the **next next** ADDC are independent.Signed-off-by: chenj Cc: linux-mips@linux-mips.orgPatchwork: https://patchwork.linux-mips.org/patch/9608/Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

3c09bae4 - MIPS: Use WSBH/DSBH/DSHD on Loongson 3A

Fri, 15 Aug 2014 08:56:58 +0000

MIPS: Use WSBH/DSBH/DSHD on Loongson 3ASigned-off-by: chenj Cc: linux-mips@linux-mips.orgCc: chenhc@lemote.comPatchwork: https://patchwork.linux-mips.org/patch/7542/Patchwork: https://patchwork.linux-mips.org/patch/7550/Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

44ba138f - MIPS: csum_partial.S CPU_DADDI_WORKAROUNDS bug fix

Fri, 04 Apr 2014 02:32:54 +0000

MIPS: csum_partial.S CPU_DADDI_WORKAROUNDS bug fixThis change reverts most of commit60724ca59eda766a30be57aec6b49bc3e2bead91 [MIPS: IP checksums: Removeunncessary .set pseudos] that introduced warnings with theCPU_DADDI_WORKAROUNDS option set:arch/mips/lib/csum_partial.S: Assembler messages:arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:467: Warning: used $3 with ".set at=$3"[...]arch/mips/lib/csum_partial.S:577: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:577: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:577: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:601: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:601: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:601: Warning: used $3 with ".set at=$3"arch/mips/lib/csum_partial.S:601: Warning: used $3 with ".set at=$3"[and so on, and so on...]The warnings are benign and good code is produced regardless because nomacros that'd use the assembler's temporary register are involved, howeverthe `.set noat' directives removed by the commit referred are crucial toguarantee this is still going to be the case after any changes in thefuture. Therefore they need to be brought back to place which thischange does.Signed-off-by: Maciej W. Rozycki Cc: linux-mips@linux-mips.orgPatchwork: https://patchwork.linux-mips.org/patch/6686/Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

6f85cebe - MIPS: lib: csum_partial: Add EVA support

Fri, 17 Jan 2014 11:36:16 +0000

MIPS: lib: csum_partial: Add EVA supportUse EVA specific functions to read and write data touser address space.Signed-off-by: Markos Chandras List of files: /linux-6.15/arch/mips/lib/csum_partial.S

e89fb56c - MIPS: lib: csum_partial: Add macro to build csum_partial symbols

Fri, 17 Jan 2014 10:48:46 +0000

MIPS: lib: csum_partial: Add macro to build csum_partial symbolsIn preparation for EVA support, we use a macro to build the__csum_partial_copy_user main code so it can be shared acrossmultiple implementations. EVA uses the same code but it replacesthe load/store/prefetch instructions with the EVA specific onestherefore using a macro avoids unnecessary code duplications.Signed-off-by: Markos Chandras List of files: /linux-6.15/arch/mips/lib/csum_partial.S

2ab82e66 - MIPS: lib: csum_partial: Merge EXC and load/store macros

Thu, 16 Jan 2014 17:02:13 +0000

MIPS: lib: csum_partial: Merge EXC and load/store macrosEach load/store macro always adds an entry to the __ex_tableusing the EXC macro. There are cases where a load instruction maynever fail such as when we are sure the load happens in the kerneladdress space. Therefore, we merge these the EXC and LOADX/STOREXmacros into a single one. We also expand the argument list in the EXCmacro to make the macro more flexible. The extra 'type' argument is notused by this commit, but it will be used when EVA support is added tomemcpy.Signed-off-by: Markos Chandras List of files: /linux-6.15/arch/mips/lib/csum_partial.S

ac85227f - MIPS: checksum: Split the 'copy_user' symbol

Thu, 12 Dec 2013 16:21:00 +0000

MIPS: checksum: Split the 'copy_user' symbolThe 'copy_user' symbol can be used to copy from or touserland so we will use two different symbols for theseoperations. This makes no difference in the existing code,but when the core is operating in EVA mode, different instructionsneed to be used to read and write to userland address space.The old function has also been renamed to 'copy_kernel' to denotethat it is suitable for copy data to and from kernel space.Signed-off-by: Markos Chandras List of files: /linux-6.15/arch/mips/lib/csum_partial.S

e744109f - MIPS: Use CONFIG_CPU_MIPSR2 in csum_partial.S

Sun, 03 Mar 2013 11:39:35 +0000

MIPS: Use CONFIG_CPU_MIPSR2 in csum_partial.SThe csum_partial implementation contain optimalizations for the MIPS R2instruction set. This optimization is never enabled however because theif directive uses the CPU_MIPSR2 constant which is not defined anywhere.Use the CONFIG_CPU_MIPSR2 constant instead.Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.orgPatchwork: https://patchwork.linux-mips.org/patch/4971/Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

70342287 - MIPS: Whitespace cleanup.

Tue, 22 Jan 2013 11:59:30 +0000

MIPS: Whitespace cleanup.Having received another series of whitespace patches I decided to do thisonce and for all rather than dealing with this kind of patches tricklingin forever.Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

b65a75b8 - MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.

Sat, 11 Oct 2008 15:18:53 +0000

MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

60724ca5 - MIPS: IP checksums: Remove unncessary .set pseudos

Sat, 11 Oct 2008 15:18:53 +0000

MIPS: IP checksums: Remove unncessary .set pseudosThey possibly silence meaningful warnings ...Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S

d86a8123 - MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.

Sat, 11 Oct 2008 15:18:53 +0000

MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.Signed-off-by: Ralf Baechle List of files: /linux-6.15/arch/mips/lib/csum_partial.S