Changes in cacheinfo.c

b62a0304 - LoongArch: Correct the cacheinfo sharing information

Sat, 25 Jan 2025 10:51:33 +0000

LoongArch: Correct the cacheinfo sharing informationSMT cores and their sibling cores share the same L1 and L2 privatecaches (of course last level cache is also shared), so correct thecacheinfo sharing information to let shared_cpu_map correctly reflectthis relationship.Below is the output of "lscpu" on Loongson-3A6000 (4 cores, 8 threads).1. Before patch: L1d: 512 KiB (8 instances) L1i: 512 KiB (8 instances) L2: 2 MiB (8 instances) L3: 16 MiB (1 instance)2. After patch: L1d: 256 KiB (4 instances) L1i: 256 KiB (4 instances) L2: 1 MiB (4 instances) L3: 16 MiB (1 instance)Reported-by: Chao Li Signed-off-by: Juxin Gao Signed-off-by: Huacai Chen List of files: /linux-6.15/arch/loongarch/kernel/cacheinfo.c

b61a40af - LoongArch: Refactor cache probe and flush methods

Wed, 12 Oct 2022 08:36:14 +0000

LoongArch: Refactor cache probe and flush methodsCurrent cache probe and flush methods have some drawbacks:1, Assume there are 3 cache levels and only 3 levels;2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.However, the fact is I + D, I + D + V, I + D + S and I + D + V + S areall valid. So, refactor the cache probe and flush methods to adapt moretypes of cache hierarchy.Signed-off-by: Huacai Chen List of files: /linux-6.15/arch/loongarch/kernel/cacheinfo.c

1aea29d7 - LoongArch: Fix shared cache size calculation

Wed, 13 Jul 2022 10:00:41 +0000

LoongArch: Fix shared cache size calculationCurrent calculation of shared cache size is from the node (die) scope,but we hope 'lscpu' to show the shared cache size of the whole packagefor multi-die chips (e.g., Loongson-3C5000L, which contains 4 dies inone package). So fix it by multiplying nodes_per_package.Signed-off-by: Huacai Chen List of files: /linux-6.15/arch/loongarch/kernel/cacheinfo.c

255b4658 - LoongArch: Fix the !CONFIG_SMP build

Sun, 05 Jun 2022 08:19:53 +0000

LoongArch: Fix the !CONFIG_SMP build1, We assume arch/loongarch/include/asm/smp.h be included in include/ linux/smp.h is valid and the reverse inclusion isn't. So remove the in arch/loongarch/include/asm/smp.h.2, arch/loongarch/include/asm/smp.h is only needed when CONFIG_SMP, and setup.c include it only because it need plat_smp_setup(). So, reorganize setup.c & smp.h, and then remove in setup.c.3, Fix cacheinfo.c and percpu.h build error by adding the missing header files when !CONFIG_SMP.4, Fix acpi.c build error by adding CONFIG_SMP guards.5, Move irq_stat definition from smp.c to irq.c and fix its declaration.6, Select CONFIG_SMP for CONFIG_NUMA, similar as other architectures do.Signed-off-by: Huacai Chen List of files: /linux-6.15/arch/loongarch/kernel/cacheinfo.c

628c3bb4 - LoongArch: Add boot and setup routines

Tue, 31 May 2022 10:04:11 +0000

LoongArch: Add boot and setup routinesAdd basic boot, setup and reset routines for LoongArch. Now, LoongArchmachines use UEFI-based firmware. The firmware passes configurationinformation to the kernel via ACPI and DMI/SMBIOS.Currently an existing interface between the kernel and the bootloaderis implemented. Kernel gets 2 values from the bootloader, passed inregisters a0 and a1; a0 is an "EFI boot flag" distinguishing UEFI andnon-UEFI firmware, while a1 is a pointer to an FDT with systable,memmap, cmdline and initrd information.The standard UEFI boot protocol (EFISTUB) will be added later.Cc: linux-efi@vger.kernel.orgCc: Ard Biesheuvel Reviewed-by: WANG Xuerui Reviewed-by: Jiaxun Yang Co-developed-by: Yun Liu Signed-off-by: Yun Liu Signed-off-by: Huacai Chen List of files: /linux-6.15/arch/loongarch/kernel/cacheinfo.c