Changes in cpucaps

2c433f70 - KVM: arm64: Compute synthetic sysreg ESR for Apple PMUv3 traps

Wed, 05 Mar 2025 20:26:36 +0000

KVM: arm64: Compute synthetic sysreg ESR for Apple PMUv3 trapsApple M* CPUs provide an IMPDEF trap for PMUv3 sysregs, where ESR_EL2.ECis a reserved value (0x3F) and a sysreg-like ISS is reported inAFSR1_EL2.Compute a synthetic ESR for these PMUv3 traps, giving the illusion ofsomething architectural to the rest of KVM.Tested-by: Janne Grunau Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20250305202641.428114-10-oliver.upton@linux.devSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

6f34024d - KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3

Wed, 05 Mar 2025 20:26:32 +0000

KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3KVM is about to learn some new tricks to virtualize PMUv3 on IMPDEFhardware. As part of that, we now need to differentiate host supportfrom guest support for PMUv3.Add a cpucap to determine if an architectural PMUv3 is present to guardhost usage of PMUv3 controls.Tested-by: Janne Grunau Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20250305202641.428114-6-oliver.upton@linux.devSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

0bc9a9e8 - KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity

Tue, 17 Dec 2024 14:23:19 +0000

KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosityIt appears that on Qualcomm's x1e CPU, CNTVOFF_EL2 doesn't reallywork, specially with HCR_EL2.E2H=1.A non-zero offset results in a screaming virtual timer interrupt,to the tune of a few 100k interrupts per second on a 4 vcpu VM.This is also evidenced by this CPU's inability to correctly runany of the timer selftests.The only case this doesn't break is when this register is set to 0,which breaks VM migration.When HCR_EL2.E2H=0, the timer seems to behave normally, and doesnot result in an interrupt storm.As a workaround, use the fact that this CPU implements FEAT_ECV,and trap all accesses to the virtual timer and counter, keepingCNTVOFF_EL2 set to zero, and emulate accesses to CVAL/TVAL/CTLand the counter itself, fixing up the timer to account for themissing offset.And if you think this is disgusting, you'd probably be right.Acked-by: Oliver Upton Link: https://lore.kernel.org/r/20241217142321.763801-12-maz@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux-6.15/arch/arm64/tools/cpucaps

efe72541 - arm64: Add support for FEAT_HAFT

Sat, 02 Nov 2024 10:42:33 +0000

arm64: Add support for FEAT_HAFTArmv8.9/v9.4 introduces the feature Hardware managed Access Flagfor Table descriptors (FEAT_HAFT). The feature is indicated byID_AA64MMFR1_EL1.HAFDBS == 0b0011 and can be enabled byTCR2_EL1.HAFT so it has a dependency on FEAT_TCR2.Adds the Kconfig for FEAT_HAFT and support detecting and enablingthe feature. The feature is enabled in __cpu_setup() before MMU onjust like HA. A CPU capability is added to notify the user of thefeature.Add definition of P{G,4,U,M}D_TABLE_AF bit and set the AF bitwhen creating the page table, which will save the hardwarefrom having to update them at runtime. This will be ignored ifFEAT_HAFT is not enabled.The AF bit of table descriptors cannot be managed by the softwareper spec, unlike the HA. So this should be used only if it's supportedsystem wide by system_supports_haft().Signed-off-by: Yicong Yang Link: https://lore.kernel.org/r/20241102104235.62560-4-yangyicong@huawei.comReviewed-by: Catalin Marinas [catalin.marinas@arm.com: added the ID check back to __cpu_setup in case of future CPU errata]Signed-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps

09e6b306 - arm64: cpufeature: discover CPU support for MPAM

Wed, 30 Oct 2024 16:03:13 +0000

arm64: cpufeature: discover CPU support for MPAMARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM)which describes an interface to cache and bandwidth controls whereverthey appear in the system.Add support to detect MPAM. Like SVE, MPAM has an extra id register thatdescribes some more properties, including the virtualisation support,which is optional. Detect this separately so we can detectmismatched/insane systems, but still use MPAM on the host even if thevirtualisation support is missing.MPAM needs enabling at the highest implemented exception level, otherwisethe register accesses trap. The 'enabled' flag is accessible to lowerexception levels, but its in a register that traps when MPAM isn't enabled.The cpufeature 'matches' hook is extended to test this on one of theCPUs, so that firmware can emulate MPAM as disabled if it is reservedfor use by secure world.Secondary CPUs that appear late could trip cpufeature's 'lower safe'behaviour after the MPAM properties have been advertised to user-space.Add a verify call to ensure late secondaries match the existing CPUs.(If you have a boot failure that bisects here its likely your CPUsadvertise MPAM in the id registers, but firmware failed to either enableor MPAM, or emulate the trap as if it were disabled)Signed-off-by: James Morse Signed-off-by: Joey Gouly Reviewed-by: Gavin Shan Tested-by: Shameer Kolothum Acked-by: Catalin Marinas Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20241030160317.2528209-4-joey.gouly@arm.comSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

6487c963 - arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS)

Tue, 01 Oct 2024 22:58:51 +0000

arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS)Add a cpufeature for GCS, allowing other code to conditionally support itat runtime.Reviewed-by: Thiago Jung Bauermann Reviewed-by: Catalin Marinas Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20241001-arm64-gcs-v13-12-222b78d87eee@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps

3496f693 - arm64: cpufeature: add Permission Overlay Extension cpucap

Thu, 22 Aug 2024 15:10:48 +0000

arm64: cpufeature: add Permission Overlay Extension cpucapThis indicates if the system supports POE. This is a CPUCAP_BOOT_CPU_FEATUREas the boot CPU will enable POE if it has it, so secondary CPUs must alsohave this feature.Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon Acked-by: Catalin Marinas Reviewed-by: Anshuman Khandual Link: https://lore.kernel.org/r/20240822151113.1479789-6-joey.gouly@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/tools/cpucaps

7187bb7d - arm64: errata: Add workaround for Arm errata 3194386 and 3312417

Wed, 08 May 2024 08:14:00 +0000

arm64: errata: Add workaround for Arm errata 3194386 and 3312417Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBSspecial-purpose register does not affect subsequent speculativeinstructions, permitting speculative store bypassing for a window oftime. This is described in their Software Developer Errata Notice (SDEN)documents:* Cortex-X4 SDEN v8.0, erratum 3194386: https://developer.arm.com/documentation/SDEN-2432808/0800/* Neoverse-V3 SDEN v6.0, erratum 3312417: https://developer.arm.com/documentation/SDEN-2891958/0600/To workaround these errata, it is necessary to place a speculationbarrier (SB) after MSR to the SSBS special-purpose register. This patchadds the requisite SB after writes to SSBS within the kernel, and hidesthe presence of SSBS from EL0 such that userspace software which caresabout SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...).Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: James Morse Cc: Will Deacon Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/tools/cpucaps

203f2b95 - arm64/fpsimd: Support FEAT_FPMR

Wed, 06 Mar 2024 23:14:48 +0000

arm64/fpsimd: Support FEAT_FPMRFEAT_FPMR defines a new EL0 accessible register FPMR use to configure theFP8 related features added to the architecture at the same time. Detectsupport for this register and context switch it for EL0 when present.Due to the sharing of responsibility for saving floating point statebetween the host kernel and KVM FP8 support is not yet implemented in KVMand a stub similar to that used for SVCR is provided for FPMR in order toavoid bisection issues. To make it easier to share host state with thehypervisor we store FPMR as a hardened usercopy field in uw (along withsome padding).Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20240306-arm64-2023-dpisa-v5-3-c568edc8ed7f@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps

9cce9c6c - arm64: mm: Handle LVA support as a CPU feature

Wed, 14 Feb 2024 12:29:11 +0000

arm64: mm: Handle LVA support as a CPU featureCurrently, we detect CPU support for 52-bit virtual addressing (LVA)extremely early, before creating the kernel page tables or enabling theMMU. We cannot override the feature this early, and so large virtualaddressing is always enabled on CPUs that implement support for it ifthe software support for it was enabled at build time. It also means werely on non-trivial code in asm to deal with this feature.Given that both the ID map and the TTBR1 mapping of the kernel image areguaranteed to be 48-bit addressable, it is not actually necessary toenable support this early, and instead, we can model it as a CPUfeature. That way, we can rely on code patching to get the correctTCR.T1SZ values programmed on secondary boot and resume from suspend.On the primary boot path, we simply enable the MMU with 48-bit virtualaddressing initially, and update TCR.T1SZ if LVA is supported from Ccode, right before creating the kernel mapping. Given that TTBR1 stillpoints to reserved_pg_dir at this point, updating TCR.T1SZ should besafe without the need for explicit TLB maintenance.Since this gets rid of all accesses to the vabits_actual variable fromasm code that occurred before TCR.T1SZ had been programmed, we no longerhave a need for this variable, and we can replace it with a C expressionthat produces the correct value directly, based on the value of TCR.T1SZ.Signed-off-by: Ard Biesheuvel Link: https://lore.kernel.org/r/20240214122845.2033971-70-ardb+git@google.comSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps

da9af507 - arm64: cpufeature: Detect HCR_EL2.NV1 being RES0

Mon, 22 Jan 2024 18:13:40 +0000

arm64: cpufeature: Detect HCR_EL2.NV1 being RES0A variant of FEAT_E2H0 not being implemented exists in the form ofHCR_EL2.E2H being RES1 *and* HCR_EL2.NV1 being RES0 (indicating thatonly VHE is supported on the host and nested guests).Add the necessary infrastructure for this new CPU capability.Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20240122181344.258974-7-maz@kernel.orgSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

546b7cde - arm64: Rename ARM64_WORKAROUND_2966298

Wed, 10 Jan 2024 17:29:20 +0000

arm64: Rename ARM64_WORKAROUND_2966298In preparation to apply ARM64_WORKAROUND_2966298 for multiple errata,rename the kconfig and capability. No functional change.Cc: stable@vger.kernel.orgSigned-off-by: Rob Herring Reviewed-by: Mark Rutland Link: https://lore.kernel.org/r/20240110-arm-errata-a510-v1-1-d02bc51aeeee@kernel.orgSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/tools/cpucaps

103423ad - arm64: Get rid of ARM64_HAS_NO_HW_PREFETCH

Wed, 22 Nov 2023 13:37:54 +0000

arm64: Get rid of ARM64_HAS_NO_HW_PREFETCHBack in 2016, it was argued that implementations lacking a HWprefetcher could be helped by sprinkling a number of PRFMinstructions in strategic locations.In 2023, the one platform that presumably needed this hack is nolonger in active use (let alone maintained), and an quickexperiment shows dropping this hack only leads to a 0.4% dropon a full kernel compilation (tested on a MT30-GS0 48 CPU system).Given that this is pretty much in the noise department and thatit may give odd ideas to other implementers, drop the hack forgood.Suggested-by: Will Deacon Suggested-by: Mark Rutland Signed-off-by: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20231122133754.1240687-1-maz@kernel.orgSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/tools/cpucaps

b1366d21 - arm64: Add ARM64_HAS_LPA2 CPU capability

Mon, 27 Nov 2023 11:17:30 +0000

arm64: Add ARM64_HAS_LPA2 CPU capabilityExpose FEAT_LPA2 as a capability so that we can take advantage ofalternatives patching in the hypervisor.Although FEAT_LPA2 presence is advertised separately for stage1 andstage2, the expectation is that in practice both stages will eithersupport or not support it. Therefore, we combine both into a singlecapability, allowing us to simplify the implementation. KVM requiressupport in both stages in order to use LPA2 since the same library isused for hyp stage 1 and guest stage 2 pgtables.Reviewed-by: Oliver Upton Signed-off-by: Ryan Roberts Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231127111737.1897081-6-ryan.roberts@arm.com List of files: /linux-6.15/arch/arm64/tools/cpucaps

34f66c4c - arm64: Use a positive cpucap for FP/SIMD

Mon, 16 Oct 2023 10:24:36 +0000

arm64: Use a positive cpucap for FP/SIMDCurrently we have a negative cpucap which describes the *absence* ofFP/SIMD rather than *presence* of FP/SIMD. This largely works, but issomewhat awkward relative to other cpucaps that describe the presence ofa feature, and it would be nicer to have a cpucap which describes thepresence of FP/SIMD:* This will allow the cpucap to be treated as a standard ARM64_CPUCAP_SYSTEM_FEATURE, which can be detected with the standard has_cpuid_feature() function and ARM64_CPUID_FIELDS() description.* This ensures that the cpucap will only transition from not-present to present, reducing the risk of unintentional and/or unsafe usage of FP/SIMD before cpucaps are finalized.* This will allow using arm64_cpu_capabilities::cpu_enable() to enable the use of FP/SIMD later, with FP/SIMD being disabled at boot time otherwise. This will ensure that any unintentional and/or unsafe usage of FP/SIMD prior to this is trapped, and will ensure that FP/SIMD is never unintentionally enabled for userspace in mismatched big.LITTLE systems.This patch replaces the negative ARM64_HAS_NO_FPSIMD cpucap with apositive ARM64_HAS_FPSIMD cpucap, making changes as described above.Note that as FP/SIMD will now be trapped when not supported system-wide,do_fpsimd_acc() must handle these traps in the same way as for SVE andSME. The commentary in fpsimd_restore_current_state() is updated todescribe the new scheme.No users of system_supports_fpsimd() need to know that FP/SIMD isavailable prior to alternatives being patched, so this is updated touse alternative_has_cap_likely() to check for the ARM64_HAS_FPSIMDcpucap, without generating code to test the system_cpucaps bitmap.Signed-off-by: Mark Rutland Reviewed-by: Mark Brown Cc: Suzuki K Poulose Cc: Will Deacon Signed-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps

471470bc - arm64: errata: Add Cortex-A520 speculative unprivileged load workaround

Thu, 21 Sep 2023 19:41:52 +0000

arm64: errata: Add Cortex-A520 speculative unprivileged load workaroundImplement the workaround for ARM Cortex-A520 erratum 2966298. On anaffected Cortex-A520 core, a speculatively executed unprivileged loadmight leak data from a privileged load via a cache side channel. Theissue only exists for loads within a translation regime with the sametranslation (e.g. same ASID and VMID). Therefore, the issue only affectsthe return to EL0.The workaround is to execute a TLBI before returning to EL0 after allloads of privileged data. A non-shareable TLBI to any address issufficient.The workaround isn't necessary if page table isolation (KPTI) isenabled, but for simplicity it will be. Page table isolation shouldnormally be disabled for Cortex-A520 as it supports the CSV3 featureand the E0PD feature (used when KASLR is enabled).Cc: stable@vger.kernel.orgSigned-off-by: Rob Herring Link: https://lore.kernel.org/r/20230921194156.1050055-2-robh@kernel.orgSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/tools/cpucaps

b206a708 - arm64: Add feature detection for fine grained traps

Tue, 15 Aug 2023 18:38:43 +0000

arm64: Add feature detection for fine grained trapsIn order to allow us to have shared code for managing fine grained trapsfor KVM guests add it as a detected feature rather than relying on itbeing a dependency of other features.Acked-by: Catalin Marinas Reviewed-by: Eric Auger Signed-off-by: Mark Brown [maz: converted to ARM64_CPUID_FIELDS()]Link: https://lore.kernel.org/r/20230301-kvm-arm64-fgt-v4-1-1bf8d235ac1f@kernel.orgReviewed-by: Zenghui Yu Reviewed-by: Miguel Luis Reviewed-by: Jing Zhang Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230815183903.2735724-10-maz@kernel.org List of files: /linux-6.15/arch/arm64/tools/cpucaps

6df696cd - arm64: errata: Mitigate Ampere1 erratum AC03_CPU_38 at stage-2

Fri, 09 Jun 2023 22:01:02 +0000

arm64: errata: Mitigate Ampere1 erratum AC03_CPU_38 at stage-2AmpereOne has an erratum in its implementation of FEAT_HAFDBS thatrequired disabling the feature on the design. This was done by reportingthe feature as not implemented in the ID register, although thecorresponding control bits were not actually RES0. This does not alignwell with the requirements of the architecture, which mandates thesebits be RES0 if HAFDBS isn't implemented.The kernel's use of stage-1 is unaffected, as the HA and HD bits areonly set if HAFDBS is detected in the ID register. KVM, on the otherhand, relies on the RES0 behavior at stage-2 to use the same value forVTCR_EL2 on any cpu in the system. Mitigate the non-RES0 behavior byleaving VTCR_EL2.HA clear on affected systems.Cc: stable@vger.kernel.orgCc: D Scott Phillips Cc: Darren Hart Acked-by: D Scott Phillips Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20230609220104.1836988-2-oliver.upton@linux.devSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

e2d6c906 - arm64: Add KVM_HVHE capability and has_hvhe() predicate

Fri, 09 Jun 2023 16:21:47 +0000

arm64: Add KVM_HVHE capability and has_hvhe() predicateExpose a capability keying the hVHE feature as well as a newpredicate testing it. Nothing is so far using it, and nothingis enabling it yet.Signed-off-by: Marc Zyngier Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20230609162200.2024064-5-maz@kernel.orgSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/tools/cpucaps

e43454c4 - arm64: cpufeature: add Permission Indirection Extension cpucap

Tue, 06 Jun 2023 14:58:46 +0000

arm64: cpufeature: add Permission Indirection Extension cpucapThis indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATUREas the boot CPU will enable PIE if it has it, so secondary CPUs must alsohave this feature.Signed-off-by: Joey Gouly Cc: Will Deacon Reviewed-by: Catalin Marinas Reviewed-by: Mark Brown Link: https://lore.kernel.org/r/20230606145859.697944-8-joey.gouly@arm.comSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/tools/cpucaps