Changes in cpu.h

09e6b306 - arm64: cpufeature: discover CPU support for MPAM

Wed, 30 Oct 2024 16:03:13 +0000

arm64: cpufeature: discover CPU support for MPAMARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM)which describes an interface to cache and bandwidth controls whereverthey appear in the system.Add support to detect MPAM. Like SVE, MPAM has an extra id register thatdescribes some more properties, including the virtualisation support,which is optional. Detect this separately so we can detectmismatched/insane systems, but still use MPAM on the host even if thevirtualisation support is missing.MPAM needs enabling at the highest implemented exception level, otherwisethe register accesses trap. The 'enabled' flag is accessible to lowerexception levels, but its in a register that traps when MPAM isn't enabled.The cpufeature 'matches' hook is extended to test this on one of theCPUs, so that firmware can emulate MPAM as disabled if it is reservedfor use by secure world.Secondary CPUs that appear late could trip cpufeature's 'lower safe'behaviour after the MPAM properties have been advertised to user-space.Add a verify call to ensure late secondaries match the existing CPUs.(If you have a boot failure that bisects here its likely your CPUsadvertise MPAM in the id registers, but firmware failed to either enableor MPAM, or emulate the trap as if it were disabled)Signed-off-by: James Morse Signed-off-by: Joey Gouly Reviewed-by: Gavin Shan Tested-by: Shameer Kolothum Acked-by: Catalin Marinas Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20241030160317.2528209-4-joey.gouly@arm.comSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

cc9f69a3 - arm64/cpufeature: Hook new identification registers up to cpufeature

Wed, 06 Mar 2024 23:14:46 +0000

arm64/cpufeature: Hook new identification registers up to cpufeatureThe 2023 architecture extensions have defined several new ID registers,hook them up to the cpufeature code so we can add feature checks and hwcapsbased on their contents.Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20240306-arm64-2023-dpisa-v5-1-c568edc8ed7f@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

805bb61f - arm64: cpufeature: Add ID_AA64MMFR4_EL1 handling

Mon, 22 Jan 2024 18:13:39 +0000

arm64: cpufeature: Add ID_AA64MMFR4_EL1 handlingAdd ID_AA64MMFR4_EL1 to the list of idregs the kernel knows about,and describe the E2H0 field.Reviewed-by: Oliver Upton Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20240122181344.258974-6-maz@kernel.orgSigned-off-by: Oliver Upton List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

d127db1a - arm64: setup: Switch over to GENERIC_CPU_DEVICES using arch_register_cpu()

Tue, 21 Nov 2023 13:44:51 +0000

arm64: setup: Switch over to GENERIC_CPU_DEVICES using arch_register_cpu()To allow ACPI's _STA value to hide CPUs that are present, but notavailable to online right now due to VMM or firmware policy, theregister_cpu() call needs to be made by the ACPI machinery when ACPIis in use. This allows it to hide CPUs that are unavailable from sysfs.Switching to GENERIC_CPU_DEVICES is an intermediate step to allow allfive ACPI architectures to be modified at once.Switch over to GENERIC_CPU_DEVICES, and provide an arch_register_cpu()that populates the hotpluggable flag. arch_register_cpu() is also theinterface the ACPI machinery expects.The struct cpu in struct cpuinfo_arm64 is never used directly, removeit to use the one GENERIC_CPU_DEVICES provides.This changes the CPUs visible in sysfs from possible to present, buton arm64 smp_prepare_cpus() ensures these are the same.This patch also has the effect of moving the registration of CPUs fromsubsys to driver core initialisation, prior to any initcalls running.Signed-off-by: James Morse Reviewed-by: "Russell King (Oracle)" Reviewed-by: Shaoqin Huang Reviewed-by: Gavin Shan Signed-off-by: "Russell King (Oracle)" Reviewed-by: Jonathan Cameron Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/E1r5R3b-00Csza-Ku@rmk-PC.armlinux.org.ukSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

39120848 - arm64/sve: Remove SMCR pseudo register from cpufeature code

Wed, 13 Sep 2023 14:48:13 +0000

arm64/sve: Remove SMCR pseudo register from cpufeature codeFor reasons that are not currently apparent during cpufeature enumerationwe maintain a pseudo register for SMCR which records the maximum supportedvector length using the value that would be written to SMCR_EL1.LEN toconfigure it. This is not exposed to userspace and is not sufficient fordetecting unsupportable configurations, we need the more detailed checks invec_update_vq_map() for that since we can't cope with missing vectorlengths on late CPUs and KVM requires an exactly matching set of supportedvector lengths as EL1 can enumerate VLs directly with the hardware.Remove the code, replacing the usage in sme_setup() with a query of thevq_map.Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20230913-arm64-vec-len-cpufeature-v1-2-cc69b0600a8a@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

abef0695 - arm64/sve: Remove ZCR pseudo register from cpufeature code

Wed, 13 Sep 2023 14:48:12 +0000

arm64/sve: Remove ZCR pseudo register from cpufeature codeFor reasons that are not currently apparent during cpufeature enumerationwe maintain a pseudo register for ZCR which records the maximum supportedvector length using the value that would be written to ZCR_EL1.LEN toconfigure it. This is not exposed to userspace and is not sufficient fordetecting unsupportable configurations, we need the more detailed checks invec_update_vq_map() for that since we can't cope with missing vectorlengths on late CPUs and KVM requires an exactly matching set of supportedvector lengths as EL1 can enumerate VLs directly with the hardware.Remove the code, replacing the usage in sve_setup() with a query of thevq_map.Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20230913-arm64-vec-len-cpufeature-v1-1-cc69b0600a8a@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

edc25898 - arm64: cpufeature: add system register ID_AA64MMFR3

Tue, 06 Jun 2023 14:58:44 +0000

arm64: cpufeature: add system register ID_AA64MMFR3Add new system register ID_AA64MMFR3 to the cpufeature infrastructure.Signed-off-by: Joey Gouly Cc: Will Deacon Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20230606145859.697944-6-joey.gouly@arm.comSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

d69d5649 - arm64/sme: Expose SMIDR through sysfs

Tue, 07 Jun 2022 13:28:57 +0000

arm64/sme: Expose SMIDR through sysfsWe currently expose MIDR and REVID to userspace through sysfs to enable itto make decisions based on the specific implementation. Since SME supportsimplementations where streaming mode is provided by a separate hardwareunit called a SMCU it provides a similar ID register SMIDR. Expose it touserspace via sysfs when the system supports SME along with the other IDregisters.Since we disable the SME priority mapping feature if it is supported byhardware we currently mask out the SMPS bit which reports that it issupported.Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220607132857.1358361-1-broonie@kernel.orgSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

b42990d3 - arm64/sme: Identify supported SME vector lengths at boot

Tue, 19 Apr 2022 11:22:17 +0000

arm64/sme: Identify supported SME vector lengths at bootThe vector lengths used for SME are controlled through a similar set ofregisters to those for SVE and enumerated using a similar algorithm withsome slight differences due to the fact that unlike SVE there are norestrictions on which combinations of vector lengths can be supportednor any mandatory vector lengths which must be implemented. Add a newvector type and implement support for enumerating it.One slightly awkward feature is that we need to read the current vectorlength using a different instruction (or enter streaming mode whichwould have the same issue and be higher cost). Rather than add an opsstructure we add special cases directly in the otherwise genericvec_probe_vqs() function, this is a bit inelegant but it's the onlyplace where this is an issue.Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20220419112247.711548-10-broonie@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

5e64b862 - arm64/sme: Basic enumeration support

Tue, 19 Apr 2022 11:22:16 +0000

arm64/sme: Basic enumeration supportThis patch introduces basic cpufeature support for discovering the presenceof the Scalable Matrix Extension.Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20220419112247.711548-9-broonie@kernel.orgSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

9e45365f - arm64: add ID_AA64ISAR2_EL1 sys register

Fri, 10 Dec 2021 16:54:31 +0000

arm64: add ID_AA64ISAR2_EL1 sys registerThis is a new ID register, introduced in 8.7.Signed-off-by: Joey Gouly Cc: Will Deacon Cc: Marc Zyngier Cc: James Morse Cc: Alexandru Elisei Cc: Suzuki K Poulose Cc: Reiji Watanabe Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.comSigned-off-by: Catalin Marinas List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

930a58b4 - arm64: cpuinfo: Split AArch32 registers out into a separate struct

Tue, 08 Jun 2021 18:02:54 +0000

arm64: cpuinfo: Split AArch32 registers out into a separate structIn preparation for late initialisation of the "sanitised" AArch32 registerstate, move the AArch32 registers out of 'struct cpuinfo' and into theirown struct definition.Acked-by: Mark Rutland Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20210608180313.11502-2-will@kernel.orgSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

21047e91 - arm64: Check if GMID_EL1.BS is the same on all CPUs

Wed, 26 May 2021 19:36:21 +0000

arm64: Check if GMID_EL1.BS is the same on all CPUsThe GMID_EL1.BS field determines the number of tags accessed by theLDGM/STGM instructions (EL1 and up), used by the kernel for copying orzeroing page tags.Taint the kernel if GMID_EL1.BS differs between CPUs but only ofCONFIG_ARM64_MTE is enabled.Signed-off-by: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Suzuki K Poulose Link: https://lore.kernel.org/r/20210526193621.21559-3-catalin.marinas@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

7513cc8a - arm64: Change the cpuinfo_arm64 member type for some sysregs to u64

Wed, 26 May 2021 19:36:20 +0000

arm64: Change the cpuinfo_arm64 member type for some sysregs to u64The architecture has been updated and the CTR_EL0, CNTFRQ_EL0,DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if mostof them have a RES0 top 32-bit.Change their type to u64 in struct cpuinfo_arm64.Signed-off-by: Catalin Marinas Cc: Will Deacon Acked-by: Mark Rutland Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210526193621.21559-2-catalin.marinas@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

d13027bb - Revert "arm64: initialize per-cpu offsets earlier"

Fri, 09 Oct 2020 10:24:17 +0000

Revert "arm64: initialize per-cpu offsets earlier"This reverts commit 353e228eb355be5a65a3c0996c774a0f46737fda.Qian Cai reports that TX2 no longer boots with his .config as it appearsthat task_cpu() gets instrumented and used before KASAN has beeninitialised.Although Mark has a proposed fix, let's take the safe option of revertingthis for now and sorting it out properly later.Link: https://lore.kernel.org/r/711bc57a314d8d646b41307008db2845b7537b3d.camel@redhat.comReported-by: Qian Cai Tested-by: Mark Rutland Signed-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

353e228e - arm64: initialize per-cpu offsets earlier

Mon, 05 Oct 2020 16:43:03 +0000

arm64: initialize per-cpu offsets earlierThe current initialization of the per-cpu offset register is difficultto follow and this initialization is not always early enough forupcoming instrumentation with KCSAN, where the instrumentation callbacksuse the per-cpu offset.To make it possible to support KCSAN, and to simplify reasoning aboutearly bringup code, let's initialize the per-cpu offset earlier, beforewe run any C code that may consume it. To do so, this patch adds a newinit_this_cpu_offset() helper that's called before the usualprimary/secondary start functions. For consistency, this is also used tore-initialize the per-cpu offset after the runtime per-cpu areas havebeen allocated (which can change CPU0's offset).So that init_this_cpu_offset() isn't subject to any instrumentation thatmight consume the per-cpu offset, it is marked with noinstr, preventinginstrumentation.Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: James Morse Cc: Will Deacon Link: https://lore.kernel.org/r/20201005164303.21389-1-mark.rutland@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

858b8a80 - arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context

Tue, 19 May 2020 09:40:54 +0000

arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 contextID_MMFR4_EL1 has been missing in the CPU context (i.e cpuinfo_arm64). Thisjust adds the register along with other required changes.Cc: Catalin Marinas Cc: Marc Zyngier Cc: Suzuki K Poulose Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.orgCc: linux-kernel@vger.kernel.orgSuggested-by: Will Deacon Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1589881254-10082-18-git-send-email-anshuman.khandual@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

152accf8 - arm64/cpufeature: Introduce ID_MMFR5 CPU register

Tue, 19 May 2020 09:40:43 +0000

arm64/cpufeature: Introduce ID_MMFR5 CPU registerThis adds basic building blocks required for ID_MMFR5 CPU register whichprovides information about the implemented memory model and memorymanagement support in AArch32 state. This is added per ARM DDI 0487F.aspecification.Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Rutland Cc: James Morse Cc: Suzuki K Poulose Cc: kvmarm@lists.cs.columbia.eduCc: linux-arm-kernel@lists.infradead.orgCc: linux-kernel@vger.kernel.orgSuggested-by: Will Deacon Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1589881254-10082-7-git-send-email-anshuman.khandual@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

dd35ec07 - arm64/cpufeature: Introduce ID_DFR1 CPU register

Tue, 19 May 2020 09:40:42 +0000

arm64/cpufeature: Introduce ID_DFR1 CPU registerThis adds basic building blocks required for ID_DFR1 CPU register whichprovides top level information about the debug system in AArch32 state.We hide the register from KVM guests, as we don't emulate the 'MTPMU'feature.This is added per ARM DDI 0487F.a specification.Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Rutland Cc: James Morse Cc: Suzuki K Poulose Cc: kvmarm@lists.cs.columbia.eduCc: linux-arm-kernel@lists.infradead.orgCc: linux-kernel@vger.kernel.orgSuggested-by: Will Deacon Reviewed-by : Suzuki K Poulose Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1589881254-10082-6-git-send-email-anshuman.khandual@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h

16824085 - arm64/cpufeature: Introduce ID_PFR2 CPU register

Tue, 19 May 2020 09:40:41 +0000

arm64/cpufeature: Introduce ID_PFR2 CPU registerThis adds basic building blocks required for ID_PFR2 CPU register whichprovides information about the AArch32 programmers model which must beinterpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is addedper ARM DDI 0487F.a specification.Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Mark Rutland Cc: James Morse Cc: Suzuki K Poulose Cc: kvmarm@lists.cs.columbia.eduCc: linux-arm-kernel@lists.infradead.orgCc: linux-kernel@vger.kernel.orgSuggested-by: Mark Rutland Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1589881254-10082-5-git-send-email-anshuman.khandual@arm.comSigned-off-by: Will Deacon List of files: /linux-6.15/arch/arm64/include/asm/cpu.h