19d3b47b - sys/mips: further adoption of SPDX licensing ID tags.

Mon, 27 Nov 2017 15:07:26 +0000

sys/mips: further adoption of SPDX licensing ID tags.Mainly focus on files that use BSD 2-Clause license, however the tool Iwas using misidentified many licenses so this was mostly a manual - errorprone - task.The Software Package Data Exchange (SPDX) group provides a specificationto make it easier for automated tools to detect and summarize well knownopensource licenses. We are gradually adopting the specification, notingthat the tags are considered only advisory and do not, in any way,superceed or replace the license texts. List of files: /freebsd-12.1/sys/mips/include/cache.h

d509eaf2 - Account for bigger secondary data cache line size.

Sat, 19 Nov 2016 16:36:38 +0000

Account for bigger secondary data cache line size.Secondary data cache line size can be bigger thanprimary data cache line size, so use biggest valueas a minimum alignment.Submitted by: kanSponsored by: DARPA, AFRL List of files: /freebsd-12.1/sys/mips/include/cache.h

c8b31c8f - Remove more unused code and declarations, and add dire warnings to the 64-bit

Mon, 12 Mar 2012 08:13:04 +0000

Remove more unused code and declarations, and add dire warnings to the 64-bitatomic ops used by 32-bit kernels. List of files: /freebsd-12.1/sys/mips/include/cache.h

30a3cd0d - Merge from projects/mips to head by hand:

Sun, 10 Jan 2010 19:50:24 +0000

Merge from projects/mips to head by hand:r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 linesRename mips_pcpu_init to mips_pcpu0_init since it applies only to theBSP. Provide a missing prototype.r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 linesGet the sense of this right. We use uintpr_t for bus_addr_t whenwe're building everything except octeon && 32-bit. As note before, weneed a clearner way, but at least now the hack is right.r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 linesAdd in Cavium's CID. Report what the unknown CID is.r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 linesInclude opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.Spell ld script name right.r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 linesAnother kludge for 64-bit bus_addr_t with 32-bit pointers...r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines- Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later- Add API for managing intrcnt/intrnames arrays- Some minor style(9) fixesr198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 linesFor XLR adds extern for its bus space routinesr198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 linesWith this commit our friend RMI will now compile. I havenot tested it and the chances of it running yet are aboutZERO.. but it will now compile. The hard part now begins, making it run ;-)r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 linesAdd some newer MIPS CO cores.r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 linesdb_expr_t is really closer to a register_t.Submitted by: bde@r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines- Remove bunch of declared but not defined cach-related variables- Add mips_picache_linesize and mips_pdcache_linesize variablesr198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 linesGet rid of the hardcoded constants to define cacheable memory:SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZEInstead we now keep a copy of the memory regions enumerated byplatform-specific code and use that to determine whether an addressis cacheable or not.r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines- Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes.r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 linesUndo spamage of last MFC.r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines_ALIGN has to return u_long, since pointers don't fit into u_int in64-bit mips.r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field- Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values.- Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current framer198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines- Get rid of label_t. It came from NetBSD and was used only in one placer198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 linesDoes 4 things:1) Adds future RMI directories2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory3) removes intr_machdep.c from files.mips4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling.r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines- Move stack tracing function to db_trace.c- Axe unused extern MipsXXX declarations- Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headersr197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines- Sync caches properly when dealing with sf_bufr196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines(u_int) is the wrong type here. Use unsigned long instead, eventhough that's only less wrong...r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 linesUse unsigned long instead of unsigned for the integer casts here. Theformer works for both ILP32 and LP64 programming models, while thelatter fails LP64.r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines- Make i/d cache size field 32-bit to prevent overflowSubmited by: Neelkanth Natur195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 linesfix prototype for MipsEmulateBranch.r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 linesBetter definitions for a few types for n32/n64.r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 linesFixed aligned macros...r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines- Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages.- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_bufr195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 linesFix atomic_store_64 prototype for 64-bit systems.r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 linesThe MCOUNT macro isn't going to work in 64-bit mode. Add a note tothis effect.r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 linesProvide a macro for PTR_ADDU as well. We may need to implement thisdifferently for N32... Use PTR_ADDU in DO_AST macro.r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 linesChange the addu here to daddu.addu paranoina prodded by: jmallet@r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 linesaddu and subu are special. We need to use daddu and dsubu here to getproper behavior.Submitted by: jmallet@r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 linesThe SB1 has cohernet memory, so add it.Also, Maxmem is better as a long.Submitted by: Neelkanth Natur195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 linesThe SB1 needs a special value for the cache field of the pte.Submitted by: Neelkanth Natur195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 linescompute the areas to save registers in for 64-bit access correctly.r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 linesFirst cut at 64-bit types. not 100% sure these are all correct forN32 ABI.r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 linesTrim unreferenced goo. SDRAM likely should be next, but it is stillreferenced.r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 linesFirst cut at atomics for 64-bit machines and SMP machines.# Note: Cavium provided a port that has atomics similar to these, but# that does a syncw; sync; atomic; sync; syncw where we just do the classic# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why# the extra is needed. Since my initial target is one core, I'll defer# investigation until I bring up multiple cores. syncw is an octeon specific# instruction.r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 linesBring in cdefs.h from NetBSD to define ABI goo.Obtained from: NetBSDr195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 linesPull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,ala sgi, and use it in preference to a bare 'la' so that it getstranslated to a 'dla' for the 64-bit pointer ABIs.r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 linesUse uintptr_t rather than unsigned here for 64-bit correctness.r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 linesDefine __ELF_WORD_SIZE appropriately for n64. Note for N32 I believethis is correct. While registers are 64-bit, n32 is a 32-bit ABI andlives in a 32-bit world (with explicit 64-bit registers, however).Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4+ SZREG' to reflect the actual offset of the structure in question.r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines(1) Use uintptr_t in preference to unsigned. The latter isn't right for64-bit case, while the former is.(2) include a SB1 specific coherency mappingSubmitted by: Neelkanth Nath (2)r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 linesdb_expr_t should be a intptr_t, not an int. These expressions can beaddresses or numbers, and that's a intptr_t if I ever saw one.r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 linesDefine COP0_SYNC for SB1 CPU.Submitted by: Neelkanth Natur195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 linesSwitch to ABI agnostic ta0-ta3. Provide defs for this in the rightplaces. Provide n32/n64 register name defintions. This should haveno effect for the O32 builds that everybody else uses, but should helpmake N64 builds possible (lots of other changes are needed for that).Obtained from: NetBSD (for the regdef.h changes)r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines- Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call.r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines- Add guards to ensure that these files are included only oncer194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines- Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1):801238b4: 2402ffff li v0,-1801238b8: c2230018 ll v1,24(s1)801238bc: 00431021 addu v0,v0,v1801238c0: e2220018 sc v0,24(s1)801238c4: 1040fffc beqz v0,801238b8 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogusr194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 linesbye bye. This is no longer referenced, but much code from it willresurface for a bus-space implementation.r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 linesCavium-specific goo is no longer necessary here. Of course, I nowhave to write a bus space for cavium, but that shouldn't be too hard.r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 linesMove this to a more approrpiate plae.r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 linesBring this in from the cavium port.r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines- Use restoreintr instead of enableint while accessing pcpu in DO_ASTr192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it.r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines- Add type cast for atomic_cmpset_acq_ptr argumentsr192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines- Remove now unused NetBSDism intr.hr192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively.r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines- Cast argument to proper type in order to avoid warnings like "shift value is too large for given type"r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines- Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities.r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines- Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places.r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 linesUse FreeBSD/arm approach for handling bus space access: space tag is a pointerto bus_space structure that defines access methods and hence every bus candefine own accessors. Default space is mips_bus_space_generic. It's a simpleinterface to physical memory, values are read with regard to host systembyte order. List of files: /freebsd-12.1/sys/mips/include/cache.h

0ffd7b67 - - Remove bunch of declared but not defined cach-related variables

Wed, 28 Oct 2009 00:01:20 +0000

- Remove bunch of declared but not defined cach-related variables- Add mips_picache_linesize and mips_pdcache_linesize variables List of files: /freebsd-12.1/sys/mips/include/cache.h

5576af82 - - Add guards to ensure that these files are included only once

Fri, 26 Jun 2009 19:54:06 +0000

- Add guards to ensure that these files are included only once List of files: /freebsd-12.1/sys/mips/include/cache.h

45d426a3 - FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,

Sun, 13 Apr 2008 07:27:37 +0000

FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,mips32r2 and mips64r2 (and close relatives) processors. Therepresently is support for ADMtek ADM5120, A mips 4Kc in a malta board,the RB533 routerboard (based on IDT RC32434) and some preliminarysupport for sibtye/broadcom designs. Other hardware support will beforthcomcing.This port boots multiuser under gxemul emulating the malta board andalso bootstraps on the hardware whose support is forthcoming...Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,Randall Stewert and others that have contributed to the mips2 and/ormips2-jnpr perforce branches. Juniper contirbuted a generic mips portlate in the life cycle of the misp2 branch. Warner Losh merged themips2 and Juniper code bases, and others list above have worked forthe past several months to get to multiuser.In addition, the mips2 work owe a debt to the trail blazing efforts ofthe original mips branch in perforce done by Juli Mallett. List of files: /freebsd-12.1/sys/mips/include/cache.h