//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file describes the VEC_* prefixed intermediate SDNodes and their // isel patterns. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// // Custom intermediate ISDs. class IsVLVT : SDTCisVT; def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, [SDTCisVec<0>, IsVLVT<2>]>>; multiclass vbrd_elem32 { // VBRDil def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)), (VBRDil (ImmCast $sy), i32:$vl)>; // VBRDrl def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)), (VBRDrl (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, SubRegIdx), i32:$vl)>; } defm : vbrd_elem32; defm : vbrd_elem32; multiclass vbrd_elem64 { // VBRDil def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)), (VBRDil (ImmCast $sy), i32:$vl)>; // VBRDrl def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)), (VBRDrl s64:$sy, i32:$vl)>; } defm : vbrd_elem64; defm : vbrd_elem64;