/* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved. * Copyright 2016 NXP * */ #ifndef _DPAA2_ETHDEV_H #define _DPAA2_ETHDEV_H #include #include #include #define DPAA2_MIN_RX_BUF_SIZE 512 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/ #define MAX_TCS DPNI_MAX_TC #define MAX_RX_QUEUES 16 #define MAX_TX_QUEUES 16 /*default tc to be used for ,congestion, distribution etc configuration. */ #define DPAA2_DEF_TC 0 /* Threshold for a Tx queue to *Enter* Congestion state. */ #define CONG_ENTER_TX_THRESHOLD 512 /* Threshold for a queue to *Exit* Congestion state. */ #define CONG_EXIT_TX_THRESHOLD 480 #define CONG_RETRY_COUNT 18000 /* RX queue tail drop threshold * currently considering 32 KB packets */ #define CONG_THRESHOLD_RX_Q (64 * 1024) #define CONG_RX_OAL 128 /* Size of the input SMMU mapped memory required by MC */ #define DIST_PARAM_IOVA_SIZE 256 /* Enable TX Congestion control support * default is disable */ #define DPAA2_TX_CGR_OFF 0x01 /* Disable RX tail drop, default is enable */ #define DPAA2_RX_TAILDROP_OFF 0x04 struct dpaa2_dev_priv { void *hw; int32_t hw_id; int32_t qdid; uint16_t token; uint8_t nb_tx_queues; uint8_t nb_rx_queues; void *rx_vq[MAX_RX_QUEUES]; void *tx_vq[MAX_TX_QUEUES]; struct dpaa2_bp_list *bp_list; /**