12     reg::{Reg, WritableReg, writable},
215     pub fn sload(&mut self, mem: AMode, rd: WritableReg, size: OperandSize, flags: MemFlags) {  in sload()  argument
220     pub fn uload(&mut self, mem: AMode, rd: WritableReg, size: OperandSize, flags: MemFlags) {  in uload()  argument
228         rd: WritableReg,  in ldr()  argument
308     pub fn mov_ir(&mut self, rd: WritableReg, imm: Imm, size: OperandSize) {  in mov_ir()  argument
336     pub fn mov_rr(&mut self, rm: Reg, rd: WritableReg, size: OperandSize) {  in mov_rr()  argument
346     pub fn fmov_rr(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in fmov_rr()  argument
363     pub fn mov_to_fpu(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in mov_to_fpu()  argument
372     pub fn mov_from_vec(&mut self, rn: Reg, rd: WritableReg, idx: u8, size: OperandSize) {  in mov_from_vec()  argument
382     pub fn add_ir(&mut self, imm: Imm12, rn: Reg, rd: WritableReg, size: OperandSize) {  in add_ir()  argument
387     pub fn adds_ir(&mut self, imm: Imm12, rn: Reg, rd: WritableReg, size: OperandSize) {  in adds_ir()  argument
392     pub fn add_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in add_rrr()  argument
401         rd: WritableReg,  in add_rrr_with_extend()  argument
409     pub fn adds_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in adds_rrr()  argument
414     pub fn addv(&mut self, rn: Reg, rd: WritableReg, size: VectorSize) {  in addv()  argument
424     pub fn sub_ir(&mut self, imm: Imm12, rn: Reg, rd: WritableReg, size: OperandSize) {  in sub_ir()  argument
434     pub fn sub_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in sub_rrr()  argument
451     pub fn mul_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in mul_rrr()  argument
524         scratch: WritableReg,  in rem_rrr()  argument
568     pub fn and_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in and_rrr()  argument
573     pub fn and_ir(&mut self, imm: ImmLogic, rn: Reg, rd: WritableReg, size: OperandSize) {  in and_ir()  argument
578     pub fn or_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in or_rrr()  argument
583     pub fn or_ir(&mut self, imm: ImmLogic, rn: Reg, rd: WritableReg, size: OperandSize) {  in or_ir()  argument
588     pub fn xor_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in xor_rrr()  argument
593     pub fn xor_ir(&mut self, imm: ImmLogic, rn: Reg, rd: WritableReg, size: OperandSize) {  in xor_ir()  argument
602         rd: WritableReg,  in shift_rrr()  argument
622         rd: WritableReg,  in shift_ir()  argument
642     pub fn clz(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in clz()  argument
647     pub fn rbit(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in rbit()  argument
652     pub fn fadd_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fadd_rrr()  argument
657     pub fn fsub_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fsub_rrr()  argument
662     pub fn fmul_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fmul_rrr()  argument
667     pub fn fdiv_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fdiv_rrr()  argument
672     pub fn fmax_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fmax_rrr()  argument
677     pub fn fmin_rrr(&mut self, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fmin_rrr()  argument
682     pub fn fneg_rr(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in fneg_rr()  argument
687     pub fn fabs_rr(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in fabs_rr()  argument
692     pub fn fsqrt_rr(&mut self, rn: Reg, rd: WritableReg, size: OperandSize) {  in fsqrt_rr()  argument
697     pub fn fround_rr(&mut self, rn: Reg, rd: WritableReg, mode: RoundingMode, size: OperandSize) {  in fround_rr()  argument
713     pub fn fushr_rri(&mut self, rn: Reg, rd: WritableReg, amount: u8, size: OperandSize) {  in fushr_rri()  argument
732         rd: WritableReg,  in fsli_rri_mod()  argument
761         rd: WritableReg,  in cvt_sint_to_float()  argument
784         rd: WritableReg,  in cvt_uint_to_float()  argument
807         rd: WritableReg,  in cvt_float_to_float()  argument
871     pub fn cset(&mut self, rd: WritableReg, cond: Cond) {  in cset()  argument
880     pub fn csel(&mut self, rn: Reg, rm: Reg, rd: WritableReg, cond: Cond) {  in csel()  argument
891     pub fn fpu_csel(&mut self, rn: Reg, rm: Reg, rd: WritableReg, cond: Cond, size: OperandSize) {  in fpu_csel()  argument
914     pub fn cnt(&mut self, rd: WritableReg) {  in cnt()  argument
923     pub fn extend(&mut self, rn: Reg, rd: WritableReg, kind: ExtendKind) {  in extend()  argument
961     fn alu_rri(&mut self, op: ALUOp, imm: Imm12, rn: Reg, rd: WritableReg, size: OperandSize) {  in alu_rri()  argument
976         rd: WritableReg,  in alu_rri_logic()  argument
993         rd: WritableReg,  in alu_rri_shift()  argument
1005     fn alu_rrr(&mut self, op: ALUOp, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in alu_rrr()  argument
1020         rd: WritableReg,  in alu_rrr_extend()  argument
1039         rd: WritableReg,  in alu_rrrr()  argument
1053     fn fpu_rrr(&mut self, op: FPUOp2, rm: Reg, rn: Reg, rd: WritableReg, size: OperandSize) {  in fpu_rrr()  argument
1063     fn fpu_rri(&mut self, op: FPUOpRI, rn: Reg, rd: WritableReg) {  in fpu_rri()  argument
1071     fn fpu_rri_mod(&mut self, op: FPUOpRIMod, ri: Reg, rn: Reg, rd: WritableReg) {  in fpu_rri_mod()  argument
1080     fn fpu_rr(&mut self, op: FPUOp1, rn: Reg, rd: WritableReg, size: OperandSize) {  in fpu_rr()  argument
1089     fn fpu_round(&mut self, op: FpuRoundMode, rn: Reg, rd: WritableReg) {  in fpu_round()  argument
1097     fn bit_rr(&mut self, op: BitOp, rn: Reg, rd: WritableReg, size: OperandSize) {  in bit_rr()  argument
1200         tmp_reg: WritableReg,  in fpu_to_int()  argument