Lines Matching refs:src
250 xmov = Xmov { dst: XReg, src: XReg };
317 xctz32 = Xctz32 { dst: XReg, src: XReg };
319 xctz64 = Xctz64 { dst: XReg, src: XReg };
322 xclz32 = Xclz32 { dst: XReg, src: XReg };
324 xclz64 = Xclz64 { dst: XReg, src: XReg };
327 xpopcnt32 = Xpopcnt32 { dst: XReg, src: XReg };
329 xpopcnt64 = Xpopcnt64 { dst: XReg, src: XReg };
368 xneg32 = Xneg32 { dst: XReg, src: XReg };
370 xneg64 = Xneg64 { dst: XReg, src: XReg };
418 xstore8_o32 = XStore8O32 { addr: AddrO32, src: XReg };
420 xstore16le_o32 = XStore16LeO32 { addr: AddrO32, src: XReg };
422 xstore32le_o32 = XStore32LeO32 { addr: AddrO32, src: XReg };
424 xstore64le_o32 = XStore64LeO32 { addr: AddrO32, src: XReg };
439 xstore8_z = XStore8Z { addr: AddrZ, src: XReg };
441 xstore16le_z = XStore16LeZ { addr: AddrZ, src: XReg };
443 xstore32le_z = XStore32LeZ { addr: AddrZ, src: XReg };
445 xstore64le_z = XStore64LeZ { addr: AddrZ, src: XReg };
460 xstore8_g32 = XStore8G32 { addr: AddrG32, src: XReg };
462 xstore16le_g32 = XStore16LeG32 { addr: AddrG32, src: XReg };
464 xstore32le_g32 = XStore32LeG32 { addr: AddrG32, src: XReg };
466 xstore64le_g32 = XStore64LeG32 { addr: AddrG32, src: XReg };
481 xstore8_g32bne = XStore8G32Bne { addr: AddrG32Bne, src: XReg };
483 xstore16le_g32bne = XStore16LeG32Bne { addr: AddrG32Bne, src: XReg };
485 xstore32le_g32bne = XStore32LeG32Bne { addr: AddrG32Bne, src: XReg };
487 xstore64le_g32bne = XStore64LeG32Bne { addr: AddrG32Bne, src: XReg };
512 zext8 = Zext8 { dst: XReg, src: XReg };
514 zext16 = Zext16 { dst: XReg, src: XReg };
516 zext32 = Zext32 { dst: XReg, src: XReg };
518 sext8 = Sext8 { dst: XReg, src: XReg };
520 sext16 = Sext16 { dst: XReg, src: XReg };
522 sext32 = Sext32 { dst: XReg, src: XReg };
525 xabs32 = XAbs32 { dst: XReg, src: XReg };
527 xabs64 = XAbs64 { dst: XReg, src: XReg };
592 xbnot32 = XBnot32 { dst: XReg, src: XReg };
594 xbnot64 = XBnot64 { dst: XReg, src: XReg };
660 bswap32 = Bswap32 { dst: XReg, src: XReg };
662 bswap64 = Bswap64 { dst: XReg, src: XReg };
680 xbmask32 = Xbmask32 { dst: XReg, src: XReg };
682 xbmask64 = Xbmask64 { dst: XReg, src: XReg };
696 xstore16be_o32 = XStore16BeO32 { addr: AddrO32, src: XReg };
698 xstore32be_o32 = XStore32BeO32 { addr: AddrO32, src: XReg };
700 xstore64be_o32 = XStore64BeO32 { addr: AddrO32, src: XReg };
710 fstore32be_o32 = Fstore32BeO32 { addr: AddrO32, src: FReg };
712 fstore64be_o32 = Fstore64BeO32 { addr: AddrO32, src: FReg };
719 fstore32le_o32 = Fstore32LeO32 { addr: AddrO32, src: FReg };
721 fstore64le_o32 = Fstore64LeO32 { addr: AddrO32, src: FReg };
728 fstore32le_z = Fstore32LeZ { addr: AddrZ, src: FReg };
730 fstore64le_z = Fstore64LeZ { addr: AddrZ, src: FReg };
737 fstore32le_g32 = Fstore32LeG32 { addr: AddrG32, src: FReg };
739 fstore64le_g32 = Fstore64LeG32 { addr: AddrG32, src: FReg };
747 vstore128le_o32 = Vstore128LeO32 { addr: AddrO32, src: VReg };
751 vstore128le_z = Vstore128LeZ { addr: AddrZ, src: VReg };
755 vstore128le_g32 = Vstore128LeG32 { addr: AddrG32, src: VReg };
758 fmov = Fmov { dst: FReg, src: FReg };
760 vmov = Vmov { dst: VReg, src: VReg };
763 bitcast_int_from_float_32 = BitcastIntFromFloat32 { dst: XReg, src: FReg };
765 bitcast_int_from_float_64 = BitcastIntFromFloat64 { dst: XReg, src: FReg };
767 bitcast_float_from_int_32 = BitcastFloatFromInt32 { dst: FReg, src: XReg };
769 bitcast_float_from_int_64 = BitcastFloatFromInt64 { dst: FReg, src: XReg };
799 f32_from_f64 = F32FromF64 { dst: FReg, src: FReg };
801 f64_from_f32 = F64FromF32 { dst: FReg, src: FReg };
804 f32_from_x32_s = F32FromX32S { dst: FReg, src: XReg };
806 f32_from_x32_u = F32FromX32U { dst: FReg, src: XReg };
808 f32_from_x64_s = F32FromX64S { dst: FReg, src: XReg };
810 f32_from_x64_u = F32FromX64U { dst: FReg, src: XReg };
812 f64_from_x32_s = F64FromX32S { dst: FReg, src: XReg };
814 f64_from_x32_u = F64FromX32U { dst: FReg, src: XReg };
816 f64_from_x64_s = F64FromX64S { dst: FReg, src: XReg };
818 f64_from_x64_u = F64FromX64U { dst: FReg, src: XReg };
821 x32_from_f32_s = X32FromF32S { dst: XReg, src: FReg };
823 x32_from_f32_u = X32FromF32U { dst: XReg, src: FReg };
825 x32_from_f64_s = X32FromF64S { dst: XReg, src: FReg };
827 x32_from_f64_u = X32FromF64U { dst: XReg, src: FReg };
829 x64_from_f32_s = X64FromF32S { dst: XReg, src: FReg };
831 x64_from_f32_u = X64FromF32U { dst: XReg, src: FReg };
833 x64_from_f64_s = X64FromF64S { dst: XReg, src: FReg };
835 x64_from_f64_u = X64FromF64U { dst: XReg, src: FReg };
838 x32_from_f32_s_sat = X32FromF32SSat { dst: XReg, src: FReg };
840 x32_from_f32_u_sat = X32FromF32USat { dst: XReg, src: FReg };
842 x32_from_f64_s_sat = X32FromF64SSat { dst: XReg, src: FReg };
844 x32_from_f64_u_sat = X32FromF64USat { dst: XReg, src: FReg };
846 x64_from_f32_s_sat = X64FromF32SSat { dst: XReg, src: FReg };
848 x64_from_f32_u_sat = X64FromF32USat { dst: XReg, src: FReg };
850 x64_from_f64_s_sat = X64FromF64SSat { dst: XReg, src: FReg };
852 x64_from_f64_u_sat = X64FromF64USat { dst: XReg, src: FReg };
878 ftrunc32 = Ftrunc32 { dst: FReg, src: FReg };
880 vtrunc32x4 = Vtrunc32x4 { dst: VReg, src: VReg };
882 vtrunc64x2 = Vtrunc64x2 { dst: VReg, src: VReg };
884 ffloor32 = Ffloor32 { dst: FReg, src: FReg };
886 vfloor32x4 = Vfloor32x4 { dst: VReg, src: VReg };
888 vfloor64x2 = Vfloor64x2 { dst: VReg, src: VReg };
890 fceil32 = Fceil32 { dst: FReg, src: FReg };
892 vceil32x4 = Vceil32x4 { dst: VReg, src: VReg };
894 vceil64x2 = Vceil64x2 { dst: VReg, src: VReg };
896 fnearest32 = Fnearest32 { dst: FReg, src: FReg };
898 fsqrt32 = Fsqrt32 { dst: FReg, src: FReg };
900 vsqrt32x4 = Vsqrt32x4 { dst: VReg, src: VReg };
902 vsqrt64x2 = Vsqrt64x2 { dst: VReg, src: VReg };
904 fneg32 = Fneg32 { dst: FReg, src: FReg };
906 vnegf32x4 = Vnegf32x4 { dst: VReg, src: VReg };
908 fabs32 = Fabs32 { dst: FReg, src: FReg };
925 ftrunc64 = Ftrunc64 { dst: FReg, src: FReg };
927 ffloor64 = Ffloor64 { dst: FReg, src: FReg };
929 fceil64 = Fceil64 { dst: FReg, src: FReg };
931 fnearest64 = Fnearest64 { dst: FReg, src: FReg };
933 vnearest32x4 = Vnearest32x4 { dst: VReg, src: VReg };
935 vnearest64x2 = Vnearest64x2 { dst: VReg, src: VReg };
937 fsqrt64 = Fsqrt64 { dst: FReg, src: FReg };
939 fneg64 = Fneg64 { dst: FReg, src: FReg };
941 fabs64 = Fabs64 { dst: FReg, src: FReg };
999 vsplatx8 = VSplatX8 { dst: VReg, src: XReg };
1001 vsplatx16 = VSplatX16 { dst: VReg, src: XReg };
1003 vsplatx32 = VSplatX32 { dst: VReg, src: XReg };
1005 vsplatx64 = VSplatX64 { dst: VReg, src: XReg };
1007 vsplatf32 = VSplatF32 { dst: VReg, src: FReg };
1009 vsplatf64 = VSplatF64 { dst: VReg, src: FReg };
1031 vbnot128 = VBnot128 { dst: VReg, src: VReg };
1036 vbitmask8x16 = Vbitmask8x16 { dst: XReg, src: VReg };
1039 vbitmask16x8 = Vbitmask16x8 { dst: XReg, src: VReg };
1042 vbitmask32x4 = Vbitmask32x4 { dst: XReg, src: VReg };
1045 vbitmask64x2 = Vbitmask64x2 { dst: XReg, src: VReg };
1047 valltrue8x16 = Valltrue8x16 { dst: XReg, src: VReg };
1049 valltrue16x8 = Valltrue16x8 { dst: XReg, src: VReg };
1051 valltrue32x4 = Valltrue32x4 { dst: XReg, src: VReg };
1053 valltrue64x2 = Valltrue64x2 { dst: XReg, src: VReg };
1055 vanytrue8x16 = Vanytrue8x16 { dst: XReg, src: VReg };
1057 vanytrue16x8 = Vanytrue16x8 { dst: XReg, src: VReg };
1059 vanytrue32x4 = Vanytrue32x4 { dst: XReg, src: VReg };
1061 vanytrue64x2 = Vanytrue64x2 { dst: XReg, src: VReg };
1064 vf32x4_from_i32x4_s = VF32x4FromI32x4S { dst: VReg, src: VReg };
1066 vf32x4_from_i32x4_u = VF32x4FromI32x4U { dst: VReg, src: VReg };
1068 vf64x2_from_i64x2_s = VF64x2FromI64x2S { dst: VReg, src: VReg };
1070 vf64x2_from_i64x2_u = VF64x2FromI64x2U { dst: VReg, src: VReg };
1072 vi32x4_from_f32x4_s = VI32x4FromF32x4S { dst: VReg, src: VReg };
1074 vi32x4_from_f32x4_u = VI32x4FromF32x4U { dst: VReg, src: VReg };
1076 vi64x2_from_f64x2_s = VI64x2FromF64x2S { dst: VReg, src: VReg };
1078 vi64x2_from_f64x2_u = VI64x2FromF64x2U { dst: VReg, src: VReg };
1082 vwidenlow8x16_s = VWidenLow8x16S { dst: VReg, src: VReg };
1085 vwidenlow8x16_u = VWidenLow8x16U { dst: VReg, src: VReg };
1088 vwidenlow16x8_s = VWidenLow16x8S { dst: VReg, src: VReg };
1091 vwidenlow16x8_u = VWidenLow16x8U { dst: VReg, src: VReg };
1094 vwidenlow32x4_s = VWidenLow32x4S { dst: VReg, src: VReg };
1097 vwidenlow32x4_u = VWidenLow32x4U { dst: VReg, src: VReg };
1100 vwidenhigh8x16_s = VWidenHigh8x16S { dst: VReg, src: VReg };
1103 vwidenhigh8x16_u = VWidenHigh8x16U { dst: VReg, src: VReg };
1106 vwidenhigh16x8_s = VWidenHigh16x8S { dst: VReg, src: VReg };
1109 vwidenhigh16x8_u = VWidenHigh16x8U { dst: VReg, src: VReg };
1112 vwidenhigh32x4_s = VWidenHigh32x4S { dst: VReg, src: VReg };
1115 vwidenhigh32x4_u = VWidenHigh32x4U { dst: VReg, src: VReg };
1139 vfpromotelow = VFpromoteLow { dst: VReg, src: VReg };
1142 vfdemote = VFdemote { dst: VReg, src: VReg };
1179 vpopcnt8x16 = VPopcnt8x16 { dst: VReg, src: VReg };
1182 xextractv8x16 = XExtractV8x16 { dst: XReg, src: VReg, lane: u8 };
1184 xextractv16x8 = XExtractV16x8 { dst: XReg, src: VReg, lane: u8 };
1186 xextractv32x4 = XExtractV32x4 { dst: XReg, src: VReg, lane: u8 };
1188 xextractv64x2 = XExtractV64x2 { dst: XReg, src: VReg, lane: u8 };
1190 fextractv32x4 = FExtractV32x4 { dst: FReg, src: VReg, lane: u8 };
1192 fextractv64x2 = FExtractV64x2 { dst: FReg, src: VReg, lane: u8 };
1257 vneg8x16 = Vneg8x16 { dst: VReg, src: VReg };
1259 vneg16x8 = Vneg16x8 { dst: VReg, src: VReg };
1261 vneg32x4 = Vneg32x4 { dst: VReg, src: VReg };
1263 vneg64x2 = Vneg64x2 { dst: VReg, src: VReg };
1265 vnegf64x2 = VnegF64x2 { dst: VReg, src: VReg };
1294 vabs8x16 = Vabs8x16 { dst: VReg, src: VReg };
1296 vabs16x8 = Vabs16x8 { dst: VReg, src: VReg };
1298 vabs32x4 = Vabs32x4 { dst: VReg, src: VReg };
1300 vabs64x2 = Vabs64x2 { dst: VReg, src: VReg };
1303 vabsf32x4 = Vabsf32x4 { dst: VReg, src: VReg };
1305 vabsf64x2 = Vabsf64x2 { dst: VReg, src: VReg };