Lines Matching refs:Opcode
260 (decl apply_div_const_magic_u32 (Opcode Value u32) Value)
265 (decl apply_div_const_magic_u32_inner (Opcode Value u32 DivConstMagicU32) Value)
281 (decl apply_div_const_magic_u32_maybe_add (Opcode Value u32 DivConstMagicU32 Value) Value)
304 (decl apply_div_const_magic_u32_maybe_shift (Opcode Value u32 DivConstMagicU32 Value) Value)
324 ;; if Opcode == Urem {
330 (decl apply_div_const_magic_u32_finish (Opcode Value u32 Value) Value)
331 (rule (apply_div_const_magic_u32_finish (Opcode.Udiv) _ _ qf) qf)
332 (rule (apply_div_const_magic_u32_finish (Opcode.Urem) numerator divisor qf)
337 (decl apply_div_const_magic_u64 (Opcode Value u64) Value)
342 (decl apply_div_const_magic_u64_inner (Opcode Value u64 DivConstMagicU64) Value)
358 (decl apply_div_const_magic_u64_maybe_add (Opcode Value u64 DivConstMagicU64 Value) Value)
381 (decl apply_div_const_magic_u64_maybe_shift (Opcode Value u64 DivConstMagicU64 Value) Value)
401 ;; if Opcode == Urem {
407 (decl apply_div_const_magic_u64_finish (Opcode Value u64 Value) Value)
408 (rule (apply_div_const_magic_u64_finish (Opcode.Udiv) _ _ qf) qf)
409 (rule (apply_div_const_magic_u64_finish (Opcode.Urem) numerator divisor qf)
415 (decl apply_div_const_magic_s32 (Opcode Value i32) Value)
421 (decl apply_div_const_magic_s32_inner (Opcode Value i32 DivConstMagicS32) Value)
437 (decl apply_div_const_magic_s32_add_sub (Opcode Value i32 DivConstMagicS32 Value) Value)
466 (decl apply_div_const_magic_s32_shift (Opcode Value i32 DivConstMagicS32 Value) Value)
481 ;; if Opcode == Srem {
487 (decl apply_div_const_magic_s32_finish (Opcode Value i32 Value) Value)
488 (rule (apply_div_const_magic_s32_finish (Opcode.Srem) numerator divisor qf)
491 (rule (apply_div_const_magic_s32_finish (Opcode.Sdiv) _numerator _divisor qf)
496 (decl apply_div_const_magic_s64 (Opcode Value i64) Value)
502 (decl apply_div_const_magic_s64_inner (Opcode Value i64 DivConstMagicS64) Value)
518 (decl apply_div_const_magic_s64_add_sub (Opcode Value i64 DivConstMagicS64 Value) Value)
547 (decl apply_div_const_magic_s64_shift (Opcode Value i64 DivConstMagicS64 Value) Value)
562 ;; if Opcode == Srem {
568 (decl apply_div_const_magic_s64_finish (Opcode Value i64 Value) Value)
569 (rule (apply_div_const_magic_s64_finish (Opcode.Srem) numerator divisor qf)
572 (rule (apply_div_const_magic_s64_finish (Opcode.Sdiv) _numerator _divisor qf)