Lines Matching refs:vector

13 ;; vector register. Fractional LMUL is used to increase the number of effective
14 ;; usable vector register groups when operating on mixed-width values.
27 ;; The tail mode specifies how the tail elements of a vector register are handled.
37 ;; The mask mode specifies how the masked elements of a vector register are handled.
353 ;; An extractor that matches any type that is known to fit in a single vector
1021 ;; This instruction splats the F register into all elements of the destination vector.
1079 ;; `vslidedown` moves all elements in the vector down by n elements.
1107 ;; This instruction copies the first element of the source vector to the destination X register.
1114 ;; This instruction copies the first element of the source vector to the destination F register.
1121 ;; This instruction copies the source X register into first element of the source vector.
1128 ;; This instruction copies the source F register into first element of the source vector.
1135 ;; This instruction splats the X register into all elements of the destination vector.
1142 ;; This instruction splats the F register into all elements of the destination vector.
1149 ;; This instruction splat's the immediate value into all elements of the destination vector.
1156 ;; This instruction merges the elements of the two source vectors into the destination vector
1157 ;; based on a mask. Elements are taken from the first source vector if the mask bit is clear,
1158 ;; and from the second source vector if the mask bit is set. This instruction is always masked.
1166 ;; Elements are taken from the first source vector if the mask bit is clear, and from the X
1175 ;; Elements are taken from the first source vector if the mask bit is clear, and from the F
1184 ;; Elements are taken from the first source vector if the mask bit is clear, and from the
1228 ;; The vector compress instruction allows elements selected by a vector mask
1229 ;; register from a source vector register group to be packed into contiguous
1230 ;; elements at the start of the destination vector register group.
1529 ;; Build a vector mask from a u64
1539 ;; the vector register.
1544 ;; Loads a `VCodeConstant` value into a vector register. For some special `VCodeConstant`s
1583 ;; Builds a vector mask corresponding to the IntCC operation.
1735 ;; Builds a vector mask corresponding to the FloatCC operation.
1884 ;; Builds the instruction sequence to round a vector register to FRM