610                 rt2: link_reg(),  in gen_prologue_frame_setup()
659                 rt2: writable_link_reg(),  in gen_epilogue_frame_restore()
763                     rt2: link_reg(),
834         while let Some([rt, rt2]) = iter.next() {
837             let rt2: Reg = rt2.to_reg().into();  localVariable
840             debug_assert!(rt2.class() == RegClass::Int);
845                 rt2,
863                         reg: rt2.to_real_reg().unwrap(),
910             let store_vec_reg_half_pair = |rt, rt2| {
916                         rt2,
928             while let Some([rt, rt2]) = iter.next() {
930                 let rt2: Reg = rt2.to_reg().into();  localVariable
933                 debug_assert_eq!(rt2.class(), RegClass::Float);
935                 let (inst, clobber_offset_change) = store_vec_reg_half_pair(rt, rt2);
950                             reg: rt2.to_real_reg().unwrap(),
1006             let load_vec_reg_half_pair = |rt, rt2| Inst::FpuLoadP64 {
1008                 rt2,
1017             while let Some([rt, rt2]) = iter.next() {
1019                 let rt2: Writable<Reg> = rt2.map(|r| r.into());  localVariable
1022                 debug_assert_eq!(rt2.to_reg().class(), RegClass::Float);
1023                 insts.push(load_vec_reg_half_pair(rt, rt2));
1038         while let Some([rt, rt2]) = iter.next() {
1040             let rt2: Writable<Reg> = rt2.map(|r| r.into());  localVariable
1043             debug_assert_eq!(rt2.to_reg().class(), RegClass::Int);
1047                 rt2,