Lines Matching refs:match
52 syn match vhdlStatement "\<\(if\|else\)\>"
53 syn match vhdlError "\<else\s\+if\>"
57 syn match vhdlType "\<bit\>\'\="
58 syn match vhdlType "\<boolean\>\'\="
59 syn match vhdlType "\<natural\>\'\="
60 syn match vhdlType "\<positive\>\'\="
61 syn match vhdlType "\<integer\>\'\="
62 syn match vhdlType "\<real\>\'\="
63 syn match vhdlType "\<time\>\'\="
65 syn match vhdlType "\<bit_vector\>\'\="
66 syn match vhdlType "\<boolean_vector\>\'\="
67 syn match vhdlType "\<integer_vector\>\'\="
68 syn match vhdlType "\<real_vector\>\'\="
69 syn match vhdlType "\<time_vector\>\'\="
71 syn match vhdlType "\<character\>\'\="
72 syn match vhdlType "\<string\>\'\="
76 syn match vhdlType "\<std_ulogic\>\'\="
77 syn match vhdlType "\<std_logic\>\'\="
78 syn match vhdlType "\<std_ulogic_vector\>\'\="
79 syn match vhdlType "\<std_logic_vector\>\'\="
80 syn match vhdlType "\<unresolved_signed\>\'\="
81 syn match vhdlType "\<unresolved_unsigned\>\'\="
82 syn match vhdlType "\<u_signed\>\'\="
83 syn match vhdlType "\<u_unsigned\>\'\="
84 syn match vhdlType "\<signed\>\'\="
85 syn match vhdlType "\<unsigned\>\'\="
89 syn match vhdlAttribute "\'high"
90 syn match vhdlAttribute "\'left"
91 syn match vhdlAttribute "\'length"
92 syn match vhdlAttribute "\'low"
93 syn match vhdlAttribute "\'range"
94 syn match vhdlAttribute "\'reverse_range"
95 syn match vhdlAttribute "\'right"
96 syn match vhdlAttribute "\'ascending"
98 syn match vhdlAttribute "\'simple_name"
99 syn match vhdlAttribute "\'instance_name"
100 syn match vhdlAttribute "\'path_name"
101 syn match vhdlAttribute "\'foreign" " VHPI
103 syn match vhdlAttribute "\'active"
104 syn match vhdlAttribute "\'delayed"
105 syn match vhdlAttribute "\'event"
106 syn match vhdlAttribute "\'last_active"
107 syn match vhdlAttribute "\'last_event"
108 syn match vhdlAttribute "\'last_value"
109 syn match vhdlAttribute "\'quiet"
110 syn match vhdlAttribute "\'stable"
111 syn match vhdlAttribute "\'transaction"
112 syn match vhdlAttribute "\'driving"
113 syn match vhdlAttribute "\'driving_value"
115 syn match vhdlAttribute "\'base"
116 syn match vhdlAttribute "\'subtype"
117 syn match vhdlAttribute "\'element"
118 syn match vhdlAttribute "\'leftof"
119 syn match vhdlAttribute "\'pos"
120 syn match vhdlAttribute "\'pred"
121 syn match vhdlAttribute "\'rightof"
122 syn match vhdlAttribute "\'succ"
123 syn match vhdlAttribute "\'val"
124 syn match vhdlAttribute "\'image"
125 syn match vhdlAttribute "\'value"
127 syn match vhdlAttribute "\'converse"
132 syn case match
134 syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
137 syn match vhdlVector "B\"[01_]\+\""
138 syn match vhdlVector "O\"[0-7_]\+\""
139 syn match vhdlVector "X\"[0-9a-f_]\+\""
140 syn match vhdlCharacter "'.'"
144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
147 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
149 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
150 syn match vhdlNumber "-\=\<\d\+\>"
151 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
152 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
160 syn match vhdlOperator "&\|+\|-\|\*\|\/"
163 syn match vhdlOperator "=\|\/=\|>\|<\|>="
166 syn match vhdlOperator "<=\|:="
167 syn match vhdlOperator "=>"
170 syn match vhdlOperator "<=>"
173 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
176 syn match vhdlOperator "<<\|>>"
180 syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
181 syn match vhdlError "[=&+\-\*\\]\+\(=\)"
184 syn match vhdlError "\(>\)[<&+\-\/\\]\+"
185 syn match vhdlError "[&+\-\/\\]\+\(>\)"
186 syn match vhdlError "\(<\)[&+\-\/\\]\+"
187 syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
191 syn match vhdlError "\(<=\)[<=&+\*\\?:]\+"
192 syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)"
193 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+"
194 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\…
195 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+"
196 syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+"
198 "syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
200 syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
201 syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
203 syn match vhdlSpecial "<>"
204 syn match vhdlSpecial "[().,;]"
208 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
209 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
211 syn case match
217 syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
220 syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/"
221 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*"
222 syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/"
223 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*"
227 syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/"
228 "syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/"
229 syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/"
230 syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/"
231 syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/"
233 syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*"
234 "syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*"
235 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*"
236 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*"
237 syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*"