Lines Matching refs:addr
16 ; CHECK-DAG: %x.addr.2.s2a = alloca i32
17 ; CHECK-DAG: %x.addr.2.phiops = alloca i32
18 ; CHECK-DAG: %x.addr.1.s2a = alloca i32
19 ; CHECK-DAG: %x.addr.1.phiops = alloca i32
20 ; CHECK-DAG: %x.addr.0.s2a = alloca i32
21 ; CHECK-DAG: %x.addr.0.phiops = alloca i32
27 ; CHECK: %x.addr.0.merge = phi i32 [ %x.addr.0.final_reload, %polly.exiting ], [ %x.addr.0,…
28 ; CHECK: ret i32 %x.addr.0.merge
31 ; CHECK-NEXT: store i32 %x, i32* %x.addr.0.phiops
35 ; CHECK: %x.addr.0.final_reload = load i32, i32* %x.addr.0.s2a
39 ; CHECK: %x.addr.0.phiops.reload[[R1:[0-9]*]] = load i32, i32* %x.addr.0.phiops
40 ; CHECK: store i32 %x.addr.0.phiops.reload[[R1]], i32* %x.addr.0.s2a
42 %x.addr.0 = phi i32 [ %x, %entry ], [ %x.addr.1, %for.inc5 ]
48 ; CHECK: %x.addr.0.s2a.reload[[R2:[0-9]*]] = load i32, i32* %x.addr.0.s2a
49 ; CHECK: store i32 %x.addr.0.s2a.reload[[R2]], i32* %x.addr.1.phiops
54 ; CHECK: %x.addr.1.s2a.reload[[R5:[0-9]*]] = load i32, i32* %x.addr.1.s2a
55 ; CHECK: store i32 %x.addr.1.s2a.reload[[R5]], i32* %x.addr.0.phiops
61 ; CHECK: %x.addr.1.phiops.reload = load i32, i32* %x.addr.1.phiops
62 ; CHECK: store i32 %x.addr.1.phiops.reload, i32* %x.addr.1.s2a
63 %x.addr.1 = phi i32 [ %x.addr.0, %for.body ], [ %x.addr.2, %for.inc ]
70 ; CHECK: %x.addr.1.s2a.reload = load i32, i32* %x.addr.1.s2a
71 ; CHECK: store i32 %x.addr.1.s2a.reload, i32* %x.addr.2.phiops
77 ; CHECK: %x.addr.2.phiops.reload = load i32, i32* %x.addr.2.phiops
78 ; CHECK: store i32 %x.addr.2.phiops.reload, i32* %x.addr.2.s2a
79 %x.addr.2 = phi i32 [ %add, %if.then ], [ %x.addr.1, %for.body3 ]
84 ; CHECK: %x.addr.2.s2a.reload[[R3:[0-9]*]] = load i32, i32* %x.addr.2.s2a
85 ; CHECK: store i32 %x.addr.2.s2a.reload[[R3]], i32* %x.addr.1.phiops
91 ; CHECK: %x.addr.1.s2a.reload[[R5:[0-9]*]] = load i32, i32* %x.addr.1.s2a
92 ; CHECK: %p_add = add nsw i32 %x.addr.1.s2a.reload[[R5]], %tmp2_p_scalar_
93 ; CHECK: store i32 %p_add, i32* %x.addr.2.phiops
96 %add = add nsw i32 %x.addr.1, %tmp2
103 ret i32 %x.addr.0