Lines Matching refs:WriteLatencies
50 std::vector<MCWriteLatencyEntry> WriteLatencies; member
58 WriteLatencies.resize(1); in SchedClassTables()
1098 std::vector<MCWriteLatencyEntry> WriteLatencies; in GenSchedClassTables() local
1181 WriteLatencies.push_back(WLEntry); in GenSchedClassTables()
1217 WriteLatencies.clear(); in GenSchedClassTables()
1239 SCDesc.NumWriteLatencyEntries = WriteLatencies.size(); in GenSchedClassTables()
1241 std::search(SchedTables.WriteLatencies.begin(), in GenSchedClassTables()
1242 SchedTables.WriteLatencies.end(), in GenSchedClassTables()
1243 WriteLatencies.begin(), WriteLatencies.end()); in GenSchedClassTables()
1244 if (WLPos != SchedTables.WriteLatencies.end()) { in GenSchedClassTables()
1245 unsigned idx = WLPos - SchedTables.WriteLatencies.begin(); in GenSchedClassTables()
1247 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i) in GenSchedClassTables()
1254 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size(); in GenSchedClassTables()
1255 llvm::append_range(SchedTables.WriteLatencies, WriteLatencies); in GenSchedClassTables()
1297 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size(); in EmitSchedClassTables()
1299 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx]; in EmitSchedClassTables()