Lines Matching refs:ProcModel
96 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
98 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
100 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
104 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
106 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
109 const CodeGenProcModel &ProcModel);
111 const CodeGenProcModel &ProcModel);
113 const CodeGenProcModel &ProcModel);
114 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
421 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
423 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second) in EmitStageAndOperandCycleData()
426 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
430 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
440 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
474 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
481 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
484 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
487 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
493 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
657 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
658 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
662 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResourceSubUnits()
663 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResourceSubUnits()
669 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc()); in EmitProcessorResourceSubUnits()
671 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
679 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, in EmitRetireControlUnitInfo() argument
682 if (Record *RCU = ProcModel.RetireControlUnit) { in EmitRetireControlUnitInfo()
693 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, in EmitRegisterFileInfo() argument
697 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
703 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
710 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, in EmitRegisterFileTables() argument
712 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { in EmitRegisterFileTables()
719 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
723 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
742 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
748 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
762 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, in EmitLoadStoreQueueInfo() argument
765 if (ProcModel.LoadQueue) { in EmitLoadStoreQueueInfo()
766 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
767 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
768 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
773 if (ProcModel.StoreQueue) { in EmitLoadStoreQueueInfo()
775 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
776 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
777 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
782 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, in EmitExtraProcessorInfo() argument
786 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
789 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
793 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
797 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), in EmitExtraProcessorInfo()
801 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
806 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources() argument
808 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
811 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
817 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResources()
818 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResources()
837 ProcModel, PRDef->getLoc()); in EmitProcessorResources()
838 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); in EmitProcessorResources()
848 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
864 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
877 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
882 "defined for processor " + ProcModel.ModelName + in FindWriteResources()
891 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
899 ProcModel.ModelName); in FindWriteResources()
907 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
917 const CodeGenProcModel &ProcModel) { in FindReadAdvance() argument
929 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
934 "defined for processor " + ProcModel.ModelName + in FindReadAdvance()
943 for (Record *RA : ProcModel.ReadAdvanceDefs) { in FindReadAdvance()
951 ProcModel.ModelName); in FindReadAdvance()
959 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1015 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables() argument
1018 if (!ProcModel.hasInstrSchedModel()) in GenSchedClassTables()
1041 if (CGT.ProcIndex == ProcModel.Index) { in GenSchedClassTables()
1056 if (!is_contained(SC.ProcIndices, ProcModel.Index)) in GenSchedClassTables()
1067 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { in GenSchedClassTables()
1081 for (Record *I : ProcModel.ItinRWDefs) { in GenSchedClassTables()
1090 LLVM_DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
1104 ProcModel); in GenSchedClassTables()
1122 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); in GenSchedClassTables()
1157 ExpandProcResources(PRVec, Cycles, ProcModel); in GenSchedClassTables()
1162 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); in GenSchedClassTables()
1188 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1449 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel() local
1450 GenSchedClassTables(ProcModel, SchedTables); in EmitSchedModel()