876       Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");  in FindWriteResources()  local
877       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindWriteResources()
907     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindWriteResources()
928       Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");  in FindReadAdvance()  local
929       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindReadAdvance()
959     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindReadAdvance()
1379       PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines "  in EmitProcessorModels()
1385     EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');  in EmitProcessorModels()
1386     EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');  in EmitProcessorModels()
1387     EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');  in EmitProcessorModels()
1388     EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');  in EmitProcessorModels()
1389     EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');  in EmitProcessorModels()
1390     EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');  in EmitProcessorModels()
1393       (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false);  in EmitProcessorModels()
1399       (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);  in EmitProcessorModels()