Lines Matching refs:CodeGenProcModel

96   unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
98 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
100 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
104 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
106 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
109 const CodeGenProcModel &ProcModel);
111 const CodeGenProcModel &ProcModel);
113 const CodeGenProcModel &ProcModel);
114 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
421 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData()
474 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData()
657 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits()
679 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, in EmitRetireControlUnitInfo()
693 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, in EmitRegisterFileInfo()
710 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, in EmitRegisterFileTables()
762 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, in EmitLoadStoreQueueInfo()
782 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, in EmitExtraProcessorInfo()
806 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources()
864 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources()
917 const CodeGenProcModel &ProcModel) { in FindReadAdvance()
970 const CodeGenProcModel &PM) { in ExpandProcResources()
1015 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables()
1371 for (const CodeGenProcModel &PM : SchedModels.procModels()) { in EmitProcessorModels()
1449 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel()