Lines Matching refs:OS
83 void debugDump(raw_ostream &OS);
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
102 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
111 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
113 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
114 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
116 OS << "namespace llvm {\n\n"; in runEnums()
118 OS << "class MCRegisterClass;\n" in runEnums()
123 OS << "namespace " << Namespace << " {\n"; in runEnums()
124 OS << "enum {\n NoRegister,\n"; in runEnums()
127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
130 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; in runEnums()
131 OS << "};\n"; in runEnums()
133 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
142 OS << "\n// Register classes\n\n"; in runEnums()
144 OS << "namespace " << Namespace << " {\n"; in runEnums()
145 OS << "enum {\n"; in runEnums()
147 OS << " " << RC.getName() << "RegClassID" in runEnums()
149 OS << "\n};\n"; in runEnums()
151 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
158 OS << "\n// Register alternate name indices\n\n"; in runEnums()
160 OS << "namespace " << Namespace << " {\n"; in runEnums()
161 OS << "enum {\n"; in runEnums()
163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
165 OS << "};\n"; in runEnums()
167 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
172 OS << "\n// Subregister indices\n\n"; in runEnums()
175 OS << "namespace " << Namespace << " {\n"; in runEnums()
176 OS << "enum : uint16_t {\n NoSubRegister,\n"; in runEnums()
179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
180 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
182 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
185 OS << "// Register pressure sets enum.\n"; in runEnums()
187 OS << "namespace " << Namespace << " {\n"; in runEnums()
188 OS << "enum RegisterPressureSets {\n"; in runEnums()
192 OS << " " << RegUnits.Name << " = " << i << ",\n"; in runEnums()
194 OS << "};\n"; in runEnums()
196 OS << "} // end namespace " << Namespace << '\n'; in runEnums()
197 OS << '\n'; in runEnums()
199 OS << "} // end namespace llvm\n\n"; in runEnums()
200 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
203 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
204 OS << Val; in printInt()
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
213 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
221 OS << '0'; in EmitRegUnitPressure()
225 OS << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
229 OS << " };\n" in EmitRegUnitPressure()
241 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
247 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
252 OS << RU.Weight << ", "; in EmitRegUnitPressure()
254 OS << "};\n" in EmitRegUnitPressure()
258 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
261 OS << "}\n\n"; in EmitRegUnitPressure()
263 OS << "\n" in EmitRegUnitPressure()
268 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
276 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
278 OS << " };\n" in EmitRegUnitPressure()
282 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
291 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
294 OS << " };\n" in EmitRegUnitPressure()
317 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
319 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
320 OS << "};\n\n"; in EmitRegUnitPressure()
322 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
327 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
330 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
332 OS << "};\n" in EmitRegUnitPressure()
336 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
343 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
347 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
350 OS << "};\n" in EmitRegUnitPressure()
383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
407 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
412 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
413 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
414 OS << I << "Dwarf2L[]"; in EmitRegMappingTables()
417 OS << " = {\n"; in EmitRegMappingTables()
430 OS << " { " << I.first << "U, " << getQualifiedName(I.second) in EmitRegMappingTables()
433 OS << "};\n"; in EmitRegMappingTables()
435 OS << ";\n"; in EmitRegMappingTables()
440 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
443 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
446 OS << ";\n\n"; in EmitRegMappingTables()
476 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
477 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
478 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
480 OS << " = {\n"; in EmitRegMappingTables()
488 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
491 OS << "};\n"; in EmitRegMappingTables()
493 OS << ";\n"; in EmitRegMappingTables()
498 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
501 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
504 OS << ";\n\n"; in EmitRegMappingTables()
510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
527 OS << " switch ("; in EmitRegMapping()
529 OS << "DwarfFlavour"; in EmitRegMapping()
531 OS << "EHFlavour"; in EmitRegMapping()
532 OS << ") {\n" in EmitRegMapping()
537 OS << " case " << i << ":\n"; in EmitRegMapping()
538 OS << " "; in EmitRegMapping()
540 OS << "RI->"; in EmitRegMapping()
545 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
547 OS << "false"; in EmitRegMapping()
549 OS << "true"; in EmitRegMapping()
550 OS << ");\n"; in EmitRegMapping()
551 OS << " break;\n"; in EmitRegMapping()
553 OS << " }\n"; in EmitRegMapping()
558 OS << " switch ("; in EmitRegMapping()
560 OS << "DwarfFlavour"; in EmitRegMapping()
562 OS << "EHFlavour"; in EmitRegMapping()
563 OS << ") {\n" in EmitRegMapping()
568 OS << " case " << i << ":\n"; in EmitRegMapping()
569 OS << " "; in EmitRegMapping()
571 OS << "RI->"; in EmitRegMapping()
576 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
578 OS << "false"; in EmitRegMapping()
580 OS << "true"; in EmitRegMapping()
581 OS << ");\n"; in EmitRegMapping()
582 OS << " break;\n"; in EmitRegMapping()
584 OS << " }\n"; in EmitRegMapping()
590 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
599 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
613 void print(raw_ostream &OS) { in print() argument
614 printBitVectorAsHex(OS, Values, 8); in print()
618 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
619 OS << getEnumName(VT); in printSimpleValueType()
622 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
623 OS << Idx->EnumValue; in printSubRegIndex()
666 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
667 OS << Val; in printDiff16()
670 static void printMask(raw_ostream &OS, LaneBitmask Val) { in printMask() argument
671 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; in printMask()
696 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
700 OS << "unsigned " << ClName in emitComposeSubRegIndices()
735 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) in emitComposeSubRegIndices()
738 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
739 OS << "\n };\n"; in emitComposeSubRegIndices()
743 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
746 OS << " { "; in emitComposeSubRegIndices()
749 OS << Rows[r][i]->getQualifiedName() << ", "; in emitComposeSubRegIndices()
751 OS << "0, "; in emitComposeSubRegIndices()
752 OS << "},\n"; in emitComposeSubRegIndices()
754 OS << " };\n\n"; in emitComposeSubRegIndices()
756 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" in emitComposeSubRegIndices()
759 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
761 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
762 OS << "}\n\n"; in emitComposeSubRegIndices()
766 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
797 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
804 OS << " "; in emitComposeSubRegIndexLaneMask()
808 printMask(OS << "{ ", P.Mask); in emitComposeSubRegIndexLaneMask()
809 OS << format(", %2u }, ", P.RotateLeft); in emitComposeSubRegIndexLaneMask()
811 OS << "{ LaneBitmask::getNone(), 0 }"; in emitComposeSubRegIndexLaneMask()
813 OS << ", "; in emitComposeSubRegIndexLaneMask()
814 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
819 OS << " };\n" in emitComposeSubRegIndexLaneMask()
823 OS << " "; in emitComposeSubRegIndexLaneMask()
824 OS << SubReg2SequenceIndexMap[i]; in emitComposeSubRegIndexLaneMask()
826 OS << ","; in emitComposeSubRegIndexLaneMask()
827 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
829 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
831 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
849 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
873 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
875 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
877 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
878 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
974 OS << "namespace llvm {\n\n"; in runMCDesc()
979 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
980 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
981 OS << "};\n\n"; in runMCDesc()
984 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
985 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); in runMCDesc()
986 OS << "};\n\n"; in runMCDesc()
989 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
990 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
991 OS << "};\n\n"; in runMCDesc()
994 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
996 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
998 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
1001 OS << "};\n\n"; in runMCDesc()
1005 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + in runMCDesc()
1008 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
1010 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
1015 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
1022 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
1026 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
1031 OS << " { "; in runMCDesc()
1034 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
1035 OS << " },\n"; in runMCDesc()
1037 OS << "};\n\n"; in runMCDesc()
1042 OS << "namespace { // Register classes...\n"; in runMCDesc()
1057 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1060 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1062 OS << "\n };\n\n"; in runMCDesc()
1064 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1070 BVE.print(OS); in runMCDesc()
1071 OS << "\n };\n\n"; in runMCDesc()
1074 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1078 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); in runMCDesc()
1080 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1092 OS << " { " << RCName << ", " << RCBitsName << ", " in runMCDesc()
1099 OS << "};\n\n"; in runMCDesc()
1101 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1104 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1105 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1107 OS << " 0,\n"; in runMCDesc()
1116 OS << " " << Value << ",\n"; in runMCDesc()
1118 OS << "};\n"; // End of HW encoding table in runMCDesc()
1121 OS << "static inline void Init" << TargetName in runMCDesc()
1135 EmitRegMapping(OS, Regs, false); in runMCDesc()
1137 OS << "}\n\n"; in runMCDesc()
1139 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1140 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1144 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1146 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1148 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1149 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1154 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1156 OS << "namespace llvm {\n\n"; in runTargetHeader()
1158 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1160 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1165 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1174 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1201 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1208 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1210 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1212 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1213 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1220 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1222 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1224 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1225 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1227 OS << "namespace llvm {\n\n"; in runTargetDesc()
1230 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1262 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1263 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1264 OS << "};\n"; in runTargetDesc()
1267 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; in runTargetDesc()
1270 OS << Idx.getName(); in runTargetDesc()
1271 OS << "\", \""; in runTargetDesc()
1273 OS << "\" };\n\n"; in runTargetDesc()
1276 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " in runTargetDesc()
1279 printMask(OS << " ", Idx.LaneMask); in runTargetDesc()
1280 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1282 OS << " };\n\n"; in runTargetDesc()
1284 OS << "\n"; in runTargetDesc()
1288 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" in runTargetDesc()
1292 OS << " // Mode = " << M << " ("; in runTargetDesc()
1294 OS << "Default"; in runTargetDesc()
1296 OS << CGH.getMode(M).Name; in runTargetDesc()
1297 OS << ")\n"; in runTargetDesc()
1303 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1308 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
1312 OS << "};\n"; in runTargetDesc()
1315 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1343 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1345 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1356 OS << "\n "; in runTargetDesc()
1357 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1358 OS << "// " << Idx.getName(); in runTargetDesc()
1361 OS << "\n};\n\n"; in runTargetDesc()
1364 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1366 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1367 OS << "};\n\n"; in runTargetDesc()
1377 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1380 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1381 OS << " nullptr\n};\n\n"; in runTargetDesc()
1387 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1395 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1397 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1398 OS << " };\n"; in runTargetDesc()
1401 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1407 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1409 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1410 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1417 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1421 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1426 printMask(OS, RC.LaneMask); in runTargetDesc()
1427 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1434 OS << "NullRegClasses,\n "; in runTargetDesc()
1436 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1438 OS << "nullptr\n"; in runTargetDesc()
1440 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1441 OS << " };\n\n"; in runTargetDesc()
1444 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1447 OS << "\nnamespace {\n"; in runTargetDesc()
1448 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; in runTargetDesc()
1450 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1451 OS << " };\n"; in runTargetDesc()
1452 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1482 OS << "\nstatic const uint8_t " in runTargetDesc()
1486 OS << AllRegCostPerUse[J] << ", "; in runTargetDesc()
1488 OS << "};\n\n"; in runTargetDesc()
1490 OS << "\nstatic const bool " in runTargetDesc()
1493 OS << (InAllocClass[I] ? "true" : "false") << ", "; in runTargetDesc()
1495 OS << "};\n\n"; in runTargetDesc()
1497 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName in runTargetDesc()
1499 OS << "CostPerUseTable, " << NumRegCosts << ", " in runTargetDesc()
1501 OS << "};\n\n"; // End of register descriptors... in runTargetDesc()
1509 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1510 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1515 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1521 OS << " static const uint8_t Table["; in runTargetDesc()
1523 OS << " static const uint16_t Table["; in runTargetDesc()
1526 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1528 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1531 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1534 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1536 OS << " },\n"; in runTargetDesc()
1538 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1545 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1548 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1549 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1550 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1551 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1552 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1553 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1554 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1555 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1557 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1559 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1561 OS << ClassName << "::\n" in runTargetDesc()
1569 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1570 OS << ", RegClassInfos, HwMode) {\n" in runTargetDesc()
1585 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1587 OS << "}\n\n"; in runTargetDesc()
1598 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1601 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1602 OS << "0 };\n"; in runTargetDesc()
1617 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1619 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1620 OS << "};\n"; in runTargetDesc()
1622 OS << "\n\n"; in runTargetDesc()
1624 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1627 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1629 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1630 OS << " };\n"; in runTargetDesc()
1631 OS << " return makeArrayRef(Masks);\n"; in runTargetDesc()
1633 OS << " return None;\n"; in runTargetDesc()
1635 OS << "}\n\n"; in runTargetDesc()
1639 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1646 OS << " " << RC->getQualifiedName() in runTargetDesc()
1650 OS << " false;\n"; in runTargetDesc()
1651 OS << "}\n\n"; in runTargetDesc()
1653 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1660 OS << " " << RC->getQualifiedName() in runTargetDesc()
1664 OS << " false;\n"; in runTargetDesc()
1665 OS << "}\n\n"; in runTargetDesc()
1667 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1674 OS << " " << RC->getQualifiedName() in runTargetDesc()
1678 OS << " false;\n"; in runTargetDesc()
1679 OS << "}\n\n"; in runTargetDesc()
1681 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1684 OS << " static const char *Names[] = {\n"; in runTargetDesc()
1686 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1687 OS << " };\n"; in runTargetDesc()
1688 OS << " return makeArrayRef(Names);\n"; in runTargetDesc()
1690 OS << " return None;\n"; in runTargetDesc()
1692 OS << "}\n\n"; in runTargetDesc()
1694 OS << "const " << TargetName << "FrameLowering *\n" << TargetName in runTargetDesc()
1700 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1701 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1704 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1707 runEnums(OS, Target, RegBank); in run()
1710 runMCDesc(OS, Target, RegBank); in run()
1713 runTargetHeader(OS, Target, RegBank); in run()
1716 runTargetDesc(OS, Target, RegBank); in run()
1722 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { in debugDump() argument
1733 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1734 OS << "\tSpillSize: {"; in debugDump()
1736 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1737 OS << " }\n\tSpillAlignment: {"; in debugDump()
1739 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1740 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1741 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1742 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1743 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1744 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1745 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1746 OS << "\tRegs:"; in debugDump()
1748 OS << " " << R->getName(); in debugDump()
1750 OS << '\n'; in debugDump()
1751 OS << "\tSubClasses:"; in debugDump()
1756 OS << " " << SRC.getName(); in debugDump()
1758 OS << '\n'; in debugDump()
1759 OS << "\tSuperClasses:"; in debugDump()
1761 OS << " " << SRC->getName(); in debugDump()
1763 OS << '\n'; in debugDump()
1767 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1768 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1769 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1773 OS << "Register " << R.getName() << ":\n"; in debugDump()
1774 OS << "\tCostPerUse: "; in debugDump()
1776 OS << Cost << " "; in debugDump()
1777 OS << '\n'; in debugDump()
1778 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
1779 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
1781 OS << "\tSubReg " << P.first->getName() in debugDump()
1789 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1790 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()